High-Level Macro-Modeling and Estimation Techniques for Switching Activity and Power Consumption

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 4, 2003, Pages 538-557

  Raghunathan, Anand ^a   Dey, Sujit ^b   Jha, Niraj K ^c  

^a NEC LABORATORIES AMERICA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Princeton University   (United States)

Author keywords

Control logic; Datapath; Glitching; Low power design; Macromodels; Micro architecture; Power estimation; Register transfer level

Indexed keywords

ENERGY UTILIZATION; ESTIMATION; MULTIPLEXING; VECTORS;

POWER CONSUMPTION;

SWITCHING;

EID: 0141638632     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.812295     Document Type: Article

References (49)

1. C. Ramachandran, F. J. Kurdahi, D. D. Gajski, A. C. H. Wu, and V. Chaiyakul, "Accurate layout area and delay modeling for system level design," in Proc. Int. Conf. Computer-Aided Design, Oct. 1992, pp. 355-361.
2. A. Kuehlmann and R. Bergamaschi, "Timing analysis in high-level synthesis," in Proc. Int. Conf. Computer-Aided Design, Nov. 1992, pp. 349-354.
3. P. K. Jha and N. D. Dutt, "Rapid estimation for parameterized components in high-level synthesis," IEEE Trans. VLSI Syst., vol. 1, pp. 296-303, Sept. 1993.
4. S. Bhattacharya, S. Dey, and F. Brglez, "Provably correct high-level timing analysis without path sensitization," in Proc. Int. Conf. Computer-Aided Design, Nov. 1994, pp. 736-742.
5. A. C. Deng, "Power analysis for CMOS/B1CMOS circuits," in Proc. Int. Workshop Low-Power Design, Apr. 1994, pp. 3-8.
6. J. Rabaey and M. Pedram, Eds., Low-Power Design Methodologies. Norwell, MA: Kluwer, 1996.
7. J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits. Norwell, MA: Kluwer, 1996.
8. M. Pedram, "Power minimization in IC design: principles and applications," ACM Trans. Design Automation Electronic Systems, vol. 1, pp. 3-56, Jan. 1996.
9. E. Macii, M. Pedram, and F. Somenzi, "High level power modeling, estimation, and optimization," in Proc. Design Automation Conf., June 1997, pp. 504-511.
10. A. R. Chandrakasan and R. W. Brodersen, Low-Power Digital CMOS Design. Norwell, MA: Kluwer, 1995.
11. J. Frenkil, "Tools and methodologies for low power design," in Proc. Design Automation Conf., June 1997, pp. 76-81.
12. W. Nebel, J. Sproch, and S. Malik, "Power analysis and optimization: spanning the levels of abstraction," in Tutorial Notes, Int. Symp. Low-Power Electronics and Design, Aug. 1997.
13. K. D. Müller-Glaser, K. Kirsch, and K. Neusinger, "Estimating essential design characteristics to support project planning for ASIC design management," in Proc. Int. Conf. Computer-Aided Design, Nov. 1991, pp. 148-151.
14. D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuits, vol. 29, pp. 663-670, June 1994.
15. D. Marculescu, R. Marculescu, and M. Pedram, "Information theoretic measures for energy consumption at the register-transfer level," in Proc. Int. Symp. Low-Power Design, Apr. 1995, pp. 81-86.
16. F. N. Najm, "Toward a high-level power estimation capability," in Proc. Int. Symp. Low-Power Design, Apr. 1995, pp. 87-92.
17. M. Nemani and F. N. Najm, "High level power estimation and the area complexity of Boolean functions," in Proc. Int. Symp. Low-Power Electronics and Design, Aug. 1996, pp. 329-334.
18. C.-H. Chen and C.-Y. Tsui, "Toward the capability of providing power-area-delay tradeoff at the register transfer level," in Proc. Int. Symp. Low-Power Electronics and Design, Aug. 1998, pp. 24-29.
19. M. Nemani and F. Najm, "High-level area and power estimation for VLSI circuits," IEEE Trans. Computer-Aided Design, vol. 18, pp. 697-713, June 1999.
20. D. D. Gajski, N. D. Dutt, A. C.-H. Wu, and S. Y.-L. Lin, High-level Synthesis: Introduction to Chip and System Design. Norwell, MA: Kluwer, 1992.
21. S. R. Powell and P. M. Chau, "Estimating power dissipation of VLSI signal processing chips: the PFA technique," in Proc. VLSI Signal Processing IV, Sept. 1990, pp. 250-259.
22. P. Landman and J. M. Rabaey, "Architectural power analysis: the dual bit type method," IEEE Trans. VLSI Syst., vol. 3, pp. 173-187, June 1995.
23. P. F. Landman and J. M. Rabaey, "Black-box capacitance models for architectural power analysis," in Proc. Int. Workshop Low-Power Design, Apr. 1994, pp. 165-170.
24. P. Landman and J. M. Rabaey, "Activity-sensitive architectural power analysis for the control path," in Proc. Int. Symp. Low-Power Design, Apr. 1995, pp. 93-98.
25. T. Sato, Y. Ootaguro, M. Nagamatsu, and H. Tago, "Evaluation of architecture-level power estimation for CMOS RISC processors," in Proc. Symp. Low-Power Electronics, Oct. 1995, pp. 44-45.
26. H. Mehta, R. M. Owens, and M. J. Irwin, "Energy characterization based on clustering," in Proc. Design Automation Conf., June 1996, pp. 702-707.
27. L. Benini, A. Bogliolo, M. Favalli, and C. De Micheli, "Regression models for behavioral power estimation," in Proc. Int. Workshop Power and Timing Modeling, Optimization, and Simulation, 1996.
28. A. Raghunathan, S. Dey, and N. K. Jha, "Register-transfer level estimation techniques for switching activity and power consumption," in Proc. Int. Conf Computer-Aided Design, Nov. 1996, pp. 158-165.
29. C. T. Hsieh, Q. Wu, C. S. Ding, and M. Pedram, "Statistical sampling and regression analysis for RT-level power evaluation," in Proc. Int. Conf. Computer-Aided Design, Nov. 1996, pp. 583-588.
30. S. Gupta and F. N. Najm, "Power macromodeling for high level power estimation," in Proc. Design Automation Conf., June 1997, pp. 365-370.
31. Z. Chen and K. Roy, "A power macromodeling technique based on power sensitivity," in Proc. Design Automation Conf., June 1998, pp. 678-683.
32. M. Barocci, L. Benini, A. Bogliolo, B. Ricco, and G. De Micheli, "Lookup table power macro-models for behavioral library components," in Proc. IEEE Alessandro Volta Memorial Workshop on Low-Power Design, Mat. 1999, pp. 173-181.
33. R. P. Llopis and F. Goossens, "The Petrol approach to high-level power estimation," in Proc. Int. Symp. Low-Power Electronics and Design, Aug. 1998, pp. 130-132.
34. D. I. Cheng, K.-T. Cheng, D. C. Wang, and M. Marek-Sadowska, "A new hybrid methodology for power estimation," in Proc. Design Automation Conf., June 1996, pp. 439-444.
35. CMOS6 Library Manual: NEC Electronics, Inc., Dec. 1992.
36. CSIM Version 5 Users Manual: Systems LSI Division, NEC Corp., 1993.
37. F. N. Najm and M. Y. Zhang, "Extreme delay sensitivity and the worst-case switching activity in VLSI circuits," in Proc. Design Automation Conf., June 1995, pp. 623-627.
38. F. N. Najm, "Transition density, a stochastic measure of activity in digital circuits," in Proc. Design Automation Conf., June 1991, pp. 642-649.
39. G. Casella and R. L. Berger, Statistical Inference. Belmont, CA: Duxbury, 1990.
40. S. M. Ross, Introduction to Probability and Statistics for Engineers and Scientists. New York: Wiley, 1987.
41. StatPlan IV Program Manual: The Futures Group, 1989.
42. M. R. Carey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. San Francisco, CA: Freeman, 1979.
43. D. E. Knuth, The Art of Computer Programming, Vol 2: Seminumerical Algorithms. Reading, MA: Addison-Wesley, 1980.
44. S. Bhattacharya, S. Dey, and F. Brglez, "Performance analysis and optimization of schedules for conditional and loop-intensive specifications," in Proc. Design Automation Conf., June 1994, pp. 491-496.
45. _, "Clock period optimization during resource sharing and assigriment," in Proc. Design Automation Conf, June 1994, pp. 195-200.
46. A. P. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. Brodersen, "Optimizing power using transformations," IEEE Trans. Computer-Aided Design, vol. 14, pp. 12-31, Jan. 1995.
47. A. Raghunathan and N. K. Jha, "SCALP: an iterative-improvement-based low-power datapath synthesis system," IEEE Trans. Computer-Aided Design, vol. 16, pp. 1260-1277, Nov. 1997.
48. J. M. Chang and M. Pedram, "Register allocation and binding far low power," in Proc. Design Automation Conf, June 1995, pp. 29-35.
49. K. S. Khouri, C. Lakshminarayana, and N. K. Jha, "High-level synthesis of low-power control-flow intensive circuits," IEEE Trans. Computer-Aided Design, vol. 18, pp. 1715-1729, Dec. 1999.