Design and CAD challenges in 45nm CMOS and beyond

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 329-333

  Frank, David J ^a   Puri, Ruchir ^a   Toma, Dorel ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Tokyo Electron US Holdings   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D TECHNOLOGY; BACK END OF LINE (BEOL); CAD INDUSTRY; CHEMICAL-MECHANICAL POLISHING (CMP); CHIP PERFORMANCE; CMOS TECHNOLOGIES; COMPUTER-AIDED DESIGN; DESIGN METHODOLOGIES; DESIGN PERFORMANCES; DEVICE STRUCTURES; DEVICE TECHNOLOGIES; EVOLUTION (CO); FRONT END OF LINE (FEOL); IC DESIGNS; INTERCONNECT STRUCTURES; INTERNATIONAL CONFERENCES; LOW TEMPERATURE (LTR); LOW-K MATERIALS; METAL GATES; NEW MATERIALS; NEW TECHNOLOGIES; PERFORMANCE IMPROVEMENTS; POWER CONSTRAINTS; SEMICONDUCTOR INDUSTRIES; TECHNOLOGY CHANGES; TECHNOLOGY OPTIMIZATION; ULTRA LOW K (ULK) MATERIALS;

CHEMICAL FINISHING; CHEMICAL MECHANICAL POLISHING; CHEMICAL POLISHING; CONSTRAINED OPTIMIZATION; DESIGN; DIELECTRIC MATERIALS; INDUSTRY; MATERIALS SCIENCE; METALS; NANOTECHNOLOGY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR MATERIALS;

TECHNOLOGY;

EID: 46149109288     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320054     Document Type: Conference Paper

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