Power-constrained device and technology design for the end of scaling

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 643-646

  Frank, David J ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CONDUCTIVITY; LOGIC GATES; OPTIMIZATION; SILICON;

POWER DISSIPATION;

CMOS INTEGRATED CIRCUITS;

EID: 0036923408     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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3. D. J. Frank, et al., Proc. 1997 ISPLED, pp. 317-22
4. A. J. Bhavnagarwala, et al., "A Minimum Total Power Methodology...," IEEE Trans VLSI Sys., 8, pp. 235-251 (2000).
5. D. J. Frank, et al., Proc. IEEE 89, pp.259-288 (2001).
6. J. C. Eble, Ph.D. Thesis, Georgia Inst. Tech., Nov. 1998.
7. D. J. Frank, "Power-constrained CMOS scaling limits," IBM J. Res. Dev. 46, pp.235-244 (2002).
8. T. S. Kuan, et al., "Fabrication and performance limits of sub 0.1 μm Cu interconnects," Mat. Res. Soc. Symp. Proc. 612, pp.D7.1.1-8 (2000).