Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 904-907

  Zhang, Lizheng ^a   Hu, Yuhen ^a   Charlie, ^b   Chen, Chungping ^b  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Interconnect Pipelining; Statistical Timing Analysis

Indexed keywords

GLOBAL INTERCONNECTS; GLOBAL WIRES; INTERCONNECT PIPELINING; STATISTICAL TIMING ANALYSIS;

ALGORITHMS; BIT ERROR RATE; DATA COMMUNICATION SYSTEMS; ELECTRIC NETWORK ANALYSIS; FREQUENCIES; LOGIC DESIGN; MONTE CARLO METHODS; PROBABILITY; STATISTICAL METHODS; THROUGHPUT;

NETWORKS (CIRCUITS);

EID: 4444289696     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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