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Volumn , Issue , 2004, Pages 904-907

Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining

Author keywords

Interconnect Pipelining; Statistical Timing Analysis

Indexed keywords

GLOBAL INTERCONNECTS; GLOBAL WIRES; INTERCONNECT PIPELINING; STATISTICAL TIMING ANALYSIS;

EID: 4444289696     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (25)

References (20)
  • 2
    • 0036866915 scopus 로고    scopus 로고
    • A power-optimal repeater insertion methodology for global interconnects in nanometer designs
    • Nov
    • K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnects in nanometer designs," IEEE Transactions on Electron Devices, vol. 49, no. 11, pp. 2001 -2007, Nov 2002.
    • (2002) IEEE Transactions on Electron Devices , vol.49 , Issue.11 , pp. 2001-2007
    • Banerjee, K.1    Mehrotra, A.2
  • 4
    • 23044525393 scopus 로고    scopus 로고
    • Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
    • July
    • C. Chu and D. F. Wong, "Closed form solutions to simultaneous buffer insertion/sizing and wire sizing," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 6, no. 3, pp. 343-371, July 2001.
    • (2001) ACM Transactions on Design Automation of Electronic Systems (TODAES) , vol.6 , Issue.3 , pp. 343-371
    • Chu, C.1    Wong, D.F.2
  • 9
    • 4444252394 scopus 로고    scopus 로고
    • Performance optimization of single-phase level sensitive circuits using time borrowing and non-zero clock skew
    • Dec
    • B. Taskin and I. S. Kourtev, "Performance optimization of single-phase level sensitive circuits using time borrowing and non-zero clock skew," TAU 2002, Dec 2002.
    • (2002) TAU 2002
    • Taskin, B.1    Kourtev, I.S.2
  • 13
    • 0033752199 scopus 로고    scopus 로고
    • Timing analysis of combinational circuits including capacitive coupling and statistical process variation
    • May
    • B. Choi and D. Walker, "Timing analysis of combinational circuits including capacitive coupling and statistical process variation," VLSI Test Symposium, 2000. Proceedings. 18th IEEE, pp. 49-54, May 2000.
    • (2000) VLSI Test Symposium, 2000. Proceedings. 18th IEEE , pp. 49-54
    • Choi, B.1    Walker, D.2
  • 17
    • 0347409182 scopus 로고    scopus 로고
    • τau: Timing analysis under uncertainty
    • Nov
    • S. Bhardwaj, S. B. Vrudhula, and D. Blaauw, "τau: Timing analysis under uncertainty," ICCAD'03, pp. 615-620, Nov 2003.
    • (2003) ICCAD'03 , pp. 615-620
    • Bhardwaj, S.1    Vrudhula, S.B.2    Blaauw, D.3
  • 18
    • 0346778721 scopus 로고    scopus 로고
    • Statistical timing analysis considering spatial correlations using a single pert-like traversal
    • Nov
    • H. Chang and S. S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single pert-like traversal," ICCAD'03, pp. 621-625, Nov 2003.
    • (2003) ICCAD'03 , pp. 621-625
    • Chang, H.1    Sapatnekar, S.S.2
  • 19
    • 0348040110 scopus 로고    scopus 로고
    • Block-based static timing analysis with uncertainty
    • Nov
    • A. Devgan and C. Kashyap, "Block-based static timing analysis with uncertainty," ICCAD'03, pp. 607-614, Nov 2003.
    • (2003) ICCAD'03 , pp. 607-614
    • Devgan, A.1    Kashyap, C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.