Timing analysis of combinational circuits including capacitive coupling and statistical process variation

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 49-54

  Choi, Byungwoo ^a   Walker, D M H ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT TESTING; MOSFET DEVICES; OPTIMIZATION;

RANDOM GATE DELAY VARIATION; STATISTICAL PROCESS VARIATION; STATISTICAL TIMING ANALYSIS;

COMBINATORIAL CIRCUITS;

EID: 0033752199     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (29)