Experience in critical path selection for deep sub-micron delay test and timing validation

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 751-756

  Liou, Jing Jia ^a   Wang, L C ^a   Krstic, A ^a   Cheng, Kwang Ting ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DEFECTS;

EVALUATION FRAMEWORK; EXPERIMENTAL ANALYSIS; PATH SELECTION STRATEGIES; PROCESS VARIATION; STATISTICAL APPROACH; STATISTICAL DELAYS; TIMING ANALYSIS; TRADITIONAL APPROACHES;

QUALITY CONTROL;

EID: 84954437245     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195120     Document Type: Conference Paper

References (17)

1. K. Baker, G. Gronthoud, M. Lousberg, I. Schanstra, , and C. Hawkins. Defect-Based Delay Testing of Resistive Vias-Contacts, A Critical Evaluation. Proceedings of IEEE International Test Conference, pages 467-476, September 1999.
2. M. A. Breuer, C. Gleason, and S. Gupta. New Validation and Test Problems for High Performance Deep Sub-Micron VLSI Circuits. Tutorial Notes, IEEE VLSI Test Symposium, April 1997.
3. Robert C. Aitken, "Nanometer Technology Effects on Fault Models for IC Testing", IEEE Computer, November 1999, pp. 46-51
4. K-T Cheng, S. Dey, M. Rodgers, and K. Roy, Test Challenges for Deep Sub-Micron Technologies, DAC 2000.
5. J.-J. Liou, A. Krstić, K.-T. Cheng, D. Mukherjee, and S. Kundu. Performance Sensitivity Analysis Using Statistical Methods and Its Applications to Delay Testing. Proceedings of Asian South Pacific Design Automation Coneference, pages 587-592, January 2000.
6. J.-J. Liou, Li-C. Wang, and K.-T. Cheng. On Theoretical and Practical Considerations of Path Selection for Delay Fault Testing. ICCAD 02.
7. W.-N. Li, S. M. Reddy, and S. K. Sahni. On Path Selection in Combinational Logic Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(1):56-63, January 1989.
8. W.-N. Li, S. M. Reddy, and S. K. Sahni. Long and Short Covering Edges in Combinational Logic Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(12):1245-1253, December 1990.
9. S. Tani, M. Teramoto, T. Fukazawa, and K. Matsuhiro. Efficient Path Selection for Delay Testing Based on Partial Path Evaluation. Proceedings of IEEE VLSI Test Symposium, pages 188-193, May 1998.
10. C. P. Ravikumar, N. Agrawal, and P. Agrawal. Hierarchical Delay Test Generation. Journal of Electronic Testing: Theory and Applications, 10(3):188-193, June 1997.
11. K. Antreich, A. Ganz, and P. Tafertshofer. Statistical Analysis of Delay Faults-Theory and Efficient Computation. AEU-International Journal of Electronics and Communications, 51(3):117-130, May 1997.
12. R. Levy, D. Blaauw, G. Braca, A. Dasgupta, A. Grinshpon, C. Oh, B. Orshav, S. Sirichotiyakul, and V. Zolotov. ClariNet: a noise analysis tool for deep submicron design. Proceedings of Design Automation Conference., pages 235-248, June 2000.
13. J.-J. Liou, K.-T. Cheng, and D. Mukherjee. Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. Proceedings of IEEE VLSI Test Symposium, pages 97-104, April 2000.
14. J.-J. Liou, Angela Krstic, Li-C. Wang, and K.-T. Cheng. False-Path-Aware Statistical Timing Analysis for Delay Test and Timing Validation. DAC June 2002.
15. A. Krstić and K.-T. Cheng. Delay Fault Testing for VLSI Circuits. Kluwer Academic Publishers, Boston, MA, 1998.
16. M. Sivaraman and A. Strojwas. Path Delay Fault Diagnosis and Coverage-A Metric and an Estimation Technique. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(3):440-457, March 2001.
17. Anacad. Eldo v4.4.x User's Manual. 1996.