Methodology and algorithms for post-placement delay optimization

Proceedings - Design Automation Conference

Volumn , Issue , 1994, Pages 327-332

  Kannan, Lalgudi N ^a   Suaris, Peter R ^a   Fang, Hong Gee ^a  

^a Escalade Corp ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTER AIDED LOGIC DESIGN; ELECTRIC WIRING; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; OPTIMIZATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; GATE ARRAY; LOGIC SYNTHESIS; METHODOLOGY;

DELAY CIRCUITS;

EID: 0028565174     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)