Combining technology mapping with post-placement resynthesis for performance optimization

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1998, Pages 616-621

  Lu, Aiguo ^a   Eisenmann, Hans ^a   Stenz, Guenter ^a   Johannes, Frank M ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; OPTIMIZATION;

LOGIC RESYNTHESIS; POST PLACEMENT DELAY;

LOGIC DESIGN;

EID: 0032304661     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)