Timing optimization on routed designs with incremental placement and routing characterization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 2, 2000, Pages 188-196

  Changfan, Chieh ^a   Hsu, Yu Chin ^a   Tsai, Fur Shing ^a  

^a University of California Riverside   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; COMPUTER AIDED DESIGN; OPTIMIZATION; TIMING CIRCUITS; VLSI CIRCUITS;

COUPLING CAPACITANCE; INCREMENTAL PLACEMENT; POST ROUTING TIMING OPTIMIZATION; ROUTED DESIGNS; TIMING OPTIMIZATION; VERY DEEP SUBMICRON;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033891168     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.828547     Document Type: Article

References (9)

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