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Volumn 2006, Issue , 2006, Pages 201-206

Timing-driven placement based on monotone cell ordering constraints

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; ELECTRIC CONDUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC WIRE; OPTIMIZATION; PROBLEM SOLVING; TIMING CIRCUITS;

EID: 33748620637     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118355     Document Type: Conference Paper
Times cited : (4)

References (22)
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  • 3
    • 4444339015 scopus 로고    scopus 로고
    • Modeling repeaters explicitly within analytical placement
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    • (2004) Proceedings of the ACM/IEEE DAC , pp. 699-704
    • Saxena, P.1    Halpin, B.2
  • 4
    • 0043136765 scopus 로고    scopus 로고
    • Timing optimization of FPGA placements by logic replication
    • G. Beraudo and J. Lillis, "Timing Optimization of FPGA Placements by Logic Replication", In Proceedings of the ACM/IEEE DAC, 196-201, 2003.
    • (2003) Proceedings of the ACM/IEEE DAC , pp. 196-201
    • Beraudo, G.1    Lillis, J.2
  • 5
    • 0036916522 scopus 로고    scopus 로고
    • Timing-driven placement using design hierarchy guided constraint generation
    • X. Yang, B. Choi and M. Sarrafzadeh, "Timing-Driven Placement using Design Hierarchy Guided Constraint Generation", In Proceedings of the IEEE ICCAD, 177-180, 2002.
    • (2002) Proceedings of the IEEE ICCAD , pp. 177-180
    • Yang, X.1    Choi, B.2    Sarrafzadeh, M.3
  • 8
    • 0038378513 scopus 로고    scopus 로고
    • Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning
    • A. B. Kahng and X. Xu, "Local Unidirectional Bias for Smooth Cutsize-Delay Tradeoff in Performance-driven bipartitioning." In ACM/IEEE ISPD, 81-86, 2003.
    • (2003) ACM/IEEE ISPD , pp. 81-86
    • Kahng, A.B.1    Xu, X.2
  • 10
    • 0348040118 scopus 로고    scopus 로고
    • Incremental placement for timing optimization
    • W. Choi and K. Bazargan, "Incremental Placement for Timing Optimization", In Proceedings of the IEEE ICCAD, 463-466, 2003.
    • (2003) Proceedings of the IEEE ICCAD , pp. 463-466
    • Choi, W.1    Bazargan, K.2
  • 16
    • 85046457769 scopus 로고
    • A linear time heuristic for improving network partitions
    • C. Fiduccia and R. Mattheyses, "A Linear Time Heuristic for Improving Network Partitions", In ACM/IEEE DAC, 175-181, 1988.
    • (1988) ACM/IEEE DAC , pp. 175-181
    • Fiduccia, C.1    Mattheyses, R.2
  • 18
    • 2942639682 scopus 로고    scopus 로고
    • FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model
    • N. Viswanathan and C. C. Chu, "FastPlace: Efficient Analytical Placement using Cell Shifting, Iterative Local refinement and a Hybrid Net Model", In Proceedings of the ACM/IEEE ISPD, 26-33, 2004.
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    • Viswanathan, N.1    Chu, C.C.2
  • 19
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    • A performance-driven standard-cell placer based on a modified force-directed algorithm
    • Y. Chou and Y. Lin, "A Performance-driven Standard-Cell Placer Based on a Modified Force-Directed Algorithm", In Proceedings of the ACM/IEEE ISPD, 24-29, 2001.
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  • 21
    • 33748583962 scopus 로고    scopus 로고
    • PMP: Performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits
    • C. Hwang and M. Pedram, "PMP: Performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits", In Proceedings of the ACM/IEEE ASP-DAC, 428-432, 2005.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.