Post-layout circuit speed-up by event elimination

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1997, Pages 211-216

  Vaishnav, Hirendu ^a   Lee, Chi Keung ^a   Pedram, Massoud ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; OPTIMIZATION;

BOOLEAN SPACE; EVENT ELIMINATION; POST LAYOUT DELAY OPTIMIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0031383437     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)