Fast Postplacement Optimization Using Functional Symmetries

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 1, 2004, Pages 102-118

  Chang, Chih Wei ^a   Hsiao, Ming Fu ^b   Hu, Bu ^c   Wang, Kai ^c   Marek Sadowska, Malgorzata ^c   Cheng, Chung Kuan ^d   Chen, Sao Jie ^e  

^a CADENCE DESIGN SYSTEMS   (United States)

^b FARADAY TECHNOLOGY CORPORATION   (Taiwan)

^c University of California   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Functional symmetry; Logic restructuring; Logic synthesis; Physical synthesis; Postlayout optimization; Timing closure

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; GRAPH THEORY; HOT CARRIERS; KINETIC ENERGY; OPTIMIZATION; PERTURBATION TECHNIQUES; TRANSCONDUCTANCE; TRANSISTORS;

FUNCTIONAL SYMMETRIES; LOGIC RESTRUCTURING; LOGIC SYNTHESIS; PHYSICAL SYNTHESIS; POSTLAYOUT OPTIMIZATION; TIMING CLOSURE;

INTEGRATED CIRCUITS;

EID: 0346500594     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.819904     Document Type: Article

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