Iterative decoder architectures

IEEE Communications Magazine

Volumn 41, Issue 8, 2003, Pages 132-140

  Yeo, Engling ^a   Nikolić, Borivoje ^a   Anantharam, Venkat ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; BIT ERROR RATE; CONSTRAINT THEORY; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; SIGNAL RECEIVERS; SIGNAL TO NOISE RATIO; TURBO CODES; VLSI CIRCUITS;

ITERATIVE DECODER; ITERATIVE DECODERS; LOG LIKELIHOOD RATIO; LOW DENSITY PARITY CHECK CODES; MESSAGE PASSING ALGORITHM;

DECODING;

EID: 0041417915     PISSN: 01636804     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCOM.2003.1222729     Document Type: Article

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