A bit-serial approximate min-sum LDPC decoder and FPGA implementation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 149-152

  Darabiha, Ahmad ^a   Carusone, Anthony Chan ^a   Kschischang, Frank R ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-SERIAL DECODING; CHECK UPDATE RULE; GEAR SHIFT DECODING; LOW-DENSITY PARITY-CHECK;

ALGORITHMS; APPROXIMATION THEORY; COMPUTATIONAL COMPLEXITY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); KNOWLEDGE ACQUISITION; PROGRAMMABLE LOGIC CONTROLLERS;

DECODING;

EID: 34547253290     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. R. G. Gallager, Low-Density Parity-Check Codes. Cambridge, MA: MIT press, 1963.
2. N. Wiberg, Codes and Decoding on General Graphs, PhD thesis. Linkoping: Linkoping University, 1996.
3. F. R. Kschischang, B. J. Frey, and H. A. Loeliger, "Factor graphs and the sum-product algorithm," IEEE Trans. on Information Theory, vol. 47, pp. 498-519, Feb. 2001.
4. F. Zarkeshvari and A. Banihashemi, "On implementation of min-sum algorithm for decoding low-density parity-check (LDPC) codes," in IEEE Globecom conference, 2002.
5. F. Lustenberger, On the Design of Analog VLSI Iterative Codes, PhD thesis. Zurich: Swiss Federal Institute of Technology, 2000.
6. E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, "VLSI architectures for iterative decoders in magnetic recording channels," IEEE Transactions on Magnetics, vol. 37. pp. 748-755, March 2001.
7. T. Zhang and K. K. Parhi, "A 54 MBPS (3, 6)-regular FPGA LDPC decoder," in IEEE Workshop on Signal Processing Systems, San Diego, CA. 2002.
8. A. J. Blanksby and C. J. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check decoder," IEEE Journal of Solid-State Circuits, vol. 37, no. 3, Mar. 2002.
9. V. Gaudet and A. Rapley, "Iterative decoding using stochastic computation," Electronics Letters, vol. 39, no. 3, pp. 299-301, February 2003.
10. M. Ardakani and F. R. Kschischang, "Gear-shift decoding," in Proc. 21st Biennial Symp. on Comm., Queen's University, Canada, 2002.
11. I. Djurdjevic, J. Xu, K. Abdel-Ghaffar, and S. Lin, "A class of low-density parity-check codes constructed based on Reed-Solomon codes with two information symbols," IEEE Comm. Letters, vol. 7, no. 7, July 2003.
12. X.-Y. Hu, E. Eleftheriou, D.-M. Arnold, and A. Dholakia, "Efficient implementation of the sum-product algorithm for decoding LDPC codes," in IEEE Global Telecommunications Conference, vol. 2, San Antonio, TX, 2001, pp. 1036-1036E.
13. A. Darabiha, A. Chan Carusone, and F. R. Kschischang, "Block-interlaced fully-parallel LDPC decoders with reduced interconnect complexity," submitted to IEEE Transactions on VLSI Systems, 2005.
14. Transmogrifier-4 Online Documentation, http://www.eecg.utoronto.ca/ ~tm4.