-
1
-
-
84890333427
-
Probability propagation and decoding in analog VLSI
-
Cambridge, MA
-
H.-A. Loeliger, F. Lustenberger, M. Helfenstein, and F. Tarköy, "Probability propagation and decoding in analog VLSI," in Pmc. Int. Symp. Information Theory, Cambridge, MA, 1998, p. 146.
-
(1998)
Pmc. Int. Symp. Information Theory
, pp. 146
-
-
Loeliger, H.-A.1
Lustenberger, F.2
Helfenstein, M.3
Tarköy, F.4
-
2
-
-
84890334273
-
The analog decoder
-
Cambridge, MA
-
J. Hagenauer and M. Winkelhofer, "The analog decoder," in Proc. Int. Symp. Information Theory, Cambridge, MA, 1998, p. 145.
-
(1998)
Proc. Int. Symp. Information Theory
, pp. 145
-
-
Hagenauer, J.1
Winkelhofer, M.2
-
3
-
-
84893737448
-
All-analog decoder for a binary (18, 9, 5) tail-biting trellis code
-
Duisburg, Germany, Sep.
-
F. Lustenberger, M. Helfenstein, G. S. Moschytz, H.-A. Loeliger, and F. Tarköy, "All-analog decoder for a binary (18, 9, 5) tail-biting trellis code," in Proc. Eur. Solid State Circuits Conf., Duisburg, Germany, Sep. 1999, pp. 362-365.
-
(1999)
Proc. Eur. Solid State Circuits Conf.
, pp. 362-365
-
-
Lustenberger, F.1
Helfenstein, M.2
Moschytz, G.S.3
Loeliger, H.-A.4
Tarköy, F.5
-
4
-
-
0034428341
-
An analog 0.25 μm BiCMOS taibiting MAP decoder
-
San Francisco, CA, Feb.
-
M. Moerz, T. Gabara, R. Yan, and J. Hagenauer, "An analog 0.25 μm BiCMOS taibiting MAP decoder," in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 2000, pp. 356-357.
-
(2000)
Proc. IEEE Int. Solid-state Circuits Conf.
, pp. 356-357
-
-
Moerz, M.1
Gabara, T.2
Yan, R.3
Hagenauer, J.4
-
5
-
-
0003448918
-
-
Ph.D. Dissertation, ETH, Zurich, Switzerland
-
F. Lustenberger, "On the Design of Analog VLSI Iterative Decoders," Ph.D. Dissertation, ETH, Zurich, Switzerland, 2000.
-
(2000)
On the Design of Analog VLSI Iterative Decoders
-
-
Lustenberger, F.1
-
6
-
-
0742286336
-
CMOS analog MAP decoder for (8,4) Hamming code
-
Jan.
-
C. Winstead, J. Dai, S. Yu, C. Myers, R. R. Harrison, and C. Schlegel, "CMOS analog MAP decoder for (8,4) Hamming code," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 122-131, Jan. 2004.
-
(2004)
IEEE J. Solid-state Circuits
, vol.39
, Issue.1
, pp. 122-131
-
-
Winstead, C.1
Dai, J.2
Yu, S.3
Myers, C.4
Harrison, R.R.5
Schlegel, C.6
-
7
-
-
0242657937
-
A 13.3-Mb/s 0.35-um CMOS analog Turbo decoder IC with a configurable interleaver
-
Nov.
-
V. C. Gaudet and P. G. Gulak, "A 13.3-Mb/s 0.35-um CMOS analog Turbo decoder IC with a configurable interleaver," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 2010-2015, Nov. 2003.
-
(2003)
IEEE J. Solid-state Circuits
, vol.38
, Issue.11
, pp. 2010-2015
-
-
Gaudet, V.C.1
Gulak, P.G.2
-
8
-
-
0027297425
-
Near Shannon limit error-correcting coding and decoding: Turbo codes
-
Geneva, Switzerland, May
-
C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error-correcting coding and decoding: Turbo Codes," in Proc. Int. Conf. Communications, Geneva, Switzerland, May 1993, pp. 1064-1070.
-
(1993)
Proc. Int. Conf. Communications
, pp. 1064-1070
-
-
Berrou, C.1
Glavieux, A.2
Thitimajshima, P.3
-
9
-
-
84925405668
-
Low density parity check codes
-
Jan.
-
R. G. Gallager, "Low density parity check codes," IRE Trans. Inform. Theory, vol. IT, pp. 21-28, Jan. 1962.
-
(1962)
IRE Trans. Inform. Theory
, vol.IT
, pp. 21-28
-
-
Gallager, R.G.1
-
10
-
-
0033099611
-
Good error-correcting codes based on very sparse matrices
-
Mar.
-
D. J. C. MacKay, "Good error-correcting codes based on very sparse matrices," IEEE Trans. Information Theory, vol. 45, no. 3, pp. 399-431, Mar. 1999.
-
(1999)
IEEE Trans. Information Theory
, vol.45
, Issue.3
, pp. 399-431
-
-
MacKay, D.J.C.1
-
11
-
-
0003643471
-
-
3G TS 25.212, v3.5.0
-
"Third Generation Partnership Project (3GPP),", 3G TS 25.212, v3.5.0, Multiplexing and Channel Coding (FDD), 2000.
-
(2000)
Multiplexing and Channel Coding (FDD)
-
-
-
12
-
-
5044250020
-
An analog Turbo decoder for the UMTS standard
-
Chicago, IL, Jun.-Jul.
-
A. Graell i Amat, S. Benedetto, G. Montorsi, D. Vogrig, A. Neviani, and A. Gerosa, "An analog Turbo decoder for the UMTS standard," in Proc. IEEE Int. Symp. Information Theory (ISIST 2004), Chicago, IL, Jun.-Jul. 2004, p. 296.
-
(2004)
Proc. IEEE Int. Symp. Information Theory (ISIST 2004)
, pp. 296
-
-
Graell i Amat, A.1
Benedetto, S.2
Montorsi, G.3
Vogrig, D.4
Neviani, A.5
Gerosa, A.6
-
13
-
-
0001901525
-
The Turbo principle: Tutorial introduction and state of the art
-
Sep.
-
J. Hagenauer, "The Turbo principle: tutorial introduction and state of the art," in Proc. Int. Symp. Turbo Codes and Rel. Topics, Sep. 1997, pp. 1-11.
-
(1997)
Proc. Int. Symp. Turbo Codes and Rel. Topics
, pp. 1-11
-
-
Hagenauer, J.1
-
14
-
-
0035246311
-
Probability propagation and decoding in analog VLSI
-
Feb.
-
H.-A. Loeliger, F. Lustenberger, M. Helfenstein, and F. Tarköy, "Probability propagation and decoding in analog VLSI," IEEE Trans. Inform. Theory, vol. 47, no. 2, pp. 837-843, Feb. 2001.
-
(2001)
IEEE Trans. Inform. Theory
, vol.47
, Issue.2
, pp. 837-843
-
-
Loeliger, H.-A.1
Lustenberger, F.2
Helfenstein, M.3
Tarköy, F.4
-
15
-
-
0032023656
-
Soft-input soft-output modules for the construction and distributed iterative decoding of code networks
-
Mar.
-
S. Benedetto, D. Divsalar, G. Montorsi, and F. Pollara, "Soft-input soft-output modules for the construction and distributed iterative decoding of code networks," Eur. Trans. Telecommun., vol. 9, pp. 155-172, Mar. 1998.
-
(1998)
Eur. Trans. Telecommun.
, vol.9
, pp. 155-172
-
-
Benedetto, S.1
Divsalar, D.2
Montorsi, G.3
Pollara, F.4
-
16
-
-
0016037512
-
Optimal decoding of linear codes for minimizing symbol error rate
-
Mar.
-
L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, "Optimal decoding of linear codes for minimizing symbol error rate," IEEE Trans. Inform. Theory, vol. 20, no. 3, pp. 284-287, Mar. 1974.
-
(1974)
IEEE Trans. Inform. Theory
, vol.20
, Issue.3
, pp. 284-287
-
-
Bahl, L.R.1
Cocke, J.2
Jelinek, F.3
Raviv, J.4
-
17
-
-
0031996386
-
Tailbiting MAP decoders
-
Feb.
-
J. B. Anderson and S. M. Hladik, "Tailbiting MAP decoders," IEEE J. Select. Areas Commun., vol. 16, no. 2, pp. 297-302, Feb. 1998.
-
(1998)
IEEE J. Select. Areas Commun.
, vol.16
, Issue.2
, pp. 297-302
-
-
Anderson, J.B.1
Hladik, S.M.2
-
18
-
-
0036292963
-
An all-analog implementation of a Turbo decoder for hard-disk drive read channels
-
May
-
A. Xotta, D. Vogrig, A. Gerosa, A. Neviani, A. Graell i Amat, G. Montorsi, M. Bruccoleri, and G. Betti, "An all-analog implementation of a Turbo decoder for hard-disk drive read channels," in Proc. Int. Symp. Circuits and Systems, May 2002, pp. V-69-V-72.
-
(2002)
Proc. Int. Symp. Circuits and Systems
-
-
Xotta, A.1
Vogrig, D.2
Gerosa, A.3
Neviani, A.4
Graell i Amat, A.5
Montorsi, G.6
Bruccoleri, M.7
Betti, G.8
-
19
-
-
84951855214
-
Analog MAP decoder for (8,4) Hamming code in sub-threshold CMOS
-
Mar.
-
C. Winstead, J. Dai, W. J. Kim, S. Little, Y.-B. Kim, C. Myers, and C. Schlegel, "Analog MAP decoder for (8,4) Hamming code in sub-threshold CMOS," in Proc. Advanced Research in VLSI Conf., Mar. 2001, pp. 132-147.
-
(2001)
Proc. Advanced Research in VLSI Conf.
, pp. 132-147
-
-
Winstead, C.1
Dai, J.2
Kim, W.J.3
Little, S.4
Kim, Y.-B.5
Myers, C.6
Schlegel, C.7
-
20
-
-
67649119451
-
A precise four-quadrant multiplier with subnanosecond response
-
Dec.
-
B. Gilbert, "A precise four-quadrant multiplier with subnanosecond response," IEEE J. Solid-State Circuits, vol. 3, no. 4, pp. 365-373, Dec. 1968.
-
(1968)
IEEE J. Solid-state Circuits
, vol.3
, Issue.4
, pp. 365-373
-
-
Gilbert, B.1
-
21
-
-
0038419807
-
Analog CMOS implementation of Gallager's iterative decoding algorithm applied to a block Turbo code
-
Bangkok, Thailand, May
-
M. Perenzoni, A. Gerosa, and A. Neviani, "Analog CMOS implementation of Gallager's iterative decoding algorithm applied to a block Turbo Code," in Proc. IEEE Int. Symp. Circuits and Systems, vol. V, Bangkok, Thailand, May 2003, pp. 813-816.
-
(2003)
Proc. IEEE Int. Symp. Circuits and Systems
, vol.5
, pp. 813-816
-
-
Perenzoni, M.1
Gerosa, A.2
Neviani, A.3
-
22
-
-
16244403881
-
Decoding and equalization: Iterative algorithms and analog networks
-
Minneapolis, MN, Aug.
-
H.-A. Loeliger, "Decoding and equalization: iterative algorithms and analog networks," presented at the IMA Talks 1999 Summer Program: Codes, Systems and Graphical Models, Minneapolis, MN, Aug. 1999.
-
(1999)
IMA Talks 1999 Summer Program: Codes, Systems and Graphical Models
-
-
Loeliger, H.-A.1
-
23
-
-
0035332876
-
Design of fixed-point iterative decoders for concatenated codes with interleavers
-
May
-
G. Montorsi and S. Benedetto, "Design of fixed-point iterative decoders for concatenated codes with interleavers," IEEE J. Select. Areas Commun., vol. 19, no. 5, pp. 871-882, May 2001.
-
(2001)
IEEE J. Select. Areas Commun.
, vol.19
, Issue.5
, pp. 871-882
-
-
Montorsi, G.1
Benedetto, S.2
-
24
-
-
16244410396
-
On the dynamics of analog asynchronous iterative decoders
-
Urbana-Champaign, IL, Oct.
-
S. Hemati and A. H. Banihashemi, "On the dynamics of analog asynchronous iterative decoders," presented at the 41st Annu. Allerton Conf. Communication, Control, and Computing, Urbana-Champaign, IL, Oct. 2003.
-
(2003)
41st Annu. Allerton Conf. Communication, Control, and Computing
-
-
Hemati, S.1
Banihashemi, A.H.2
-
25
-
-
84888032339
-
On mismatch errors in analog-VLSI error correcting decoders
-
Sydney, Australia, May
-
F. Lustenberger and H.-A. Loeliger, "On mismatch errors in analog-VLSI error correcting decoders," in Proc. Int. Symp. Circuits and Systems, vol. IV, Sydney, Australia, May 2001, pp. 198-201.
-
(2001)
Proc. Int. Symp. Circuits and Systems
, vol.4
, pp. 198-201
-
-
Lustenberger, F.1
Loeliger, H.-A.2
-
27
-
-
0036857198
-
A unified Turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18 μm CMOS
-
Nov.
-
M. A. Bickerstaff, D. Garrett, T. Prokop, C. Thomas, B. Widdup, G. Zhou, L. M. Davis, G. Woodward, C. Nicol, and R.-H. Yan, "A unified Turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18 μm CMOS," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1555-1564, Nov. 2002.
-
(2002)
IEEE J. Solid-state Circuits
, vol.37
, Issue.11
, pp. 1555-1564
-
-
Bickerstaff, M.A.1
Garrett, D.2
Prokop, T.3
Thomas, C.4
Widdup, B.5
Zhou, G.6
Davis, L.M.7
Woodward, G.8
Nicol, C.9
Yan, R.-H.10
-
28
-
-
0037630985
-
A 24 Mb/s radix-4 logMAP Turbo decoder for 3GPP-HSDPA mobile wireless
-
San Francisco, CA, Feb.
-
M. A. Bickerstaff, L. M. Davis, C. Thomas, D. Garrett, and C. Nicol, "A 24 Mb/s radix-4 logMAP Turbo decoder for 3GPP-HSDPA mobile wireless," in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 2003, pp. 150-151.
-
(2003)
Proc. IEEE Int. Solid-state Circuits Conf.
, pp. 150-151
-
-
Bickerstaff, M.A.1
Davis, L.M.2
Thomas, C.3
Garrett, D.4
Nicol, C.5
-
29
-
-
1642451660
-
Analog sliding window decoder for mixed signal Turbo decoder
-
Erlangen, Feb.
-
M. Moerz, "Analog sliding window decoder for mixed signal Turbo decoder," in Proc. ITG Conf. Source and Channel Coding, Erlangen, Feb. 2004. pp. 63-70.
-
(2004)
Proc. ITG Conf. Source and Channel Coding
, pp. 63-70
-
-
Moerz, M.1
-
30
-
-
2442614806
-
Design and decoding of optimal high-rate convolutional codes
-
May
-
A. Graell i Amat, G. Montorsi, and S. Benedetto, "Design and decoding of optimal high-rate convolutional codes," IEEE Trans. Inform. Theory, vol. 50, no. 3, pp. 867-881, May 2004.
-
(2004)
IEEE Trans. Inform. Theory
, vol.50
, Issue.3
, pp. 867-881
-
-
Graell i Amat, A.1
Montorsi, G.2
Benedetto, S.3
-
31
-
-
0036663286
-
Programmable interleaver design for analog iterative decoders
-
Jul.
-
V. C. Gaudet, R. J. Gaudet, and P. G. Gulak, "Programmable interleaver design for analog iterative decoders," IEEE Trans. Circuits Syst. II, vol. 49, no. 7, pp. 457-464, Jul. 2002.
-
(2002)
IEEE Trans. Circuits Syst. II
, vol.49
, Issue.7
, pp. 457-464
-
-
Gaudet, V.C.1
Gaudet, R.J.2
Gulak, P.G.3
|