An improved pipelined MSB-first add-compare select unit structure for Viterbi decoders

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 51, Issue 3, 2004, Pages 504-511

  Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CONVOLUTIONAL CODES; DATA COMMUNICATION SYSTEMS; DIGITAL ARITHMETIC; PIPELINE PROCESSING SYSTEMS; TRELLIS CODES;

ADD COMPARE SELECT; MOST SIGNIFICANT BIT FIRST; PIPELINING; REDUNDANT ARITHMETIC; VITERBI DECODERS;

DECODING;

EID: 4544227360     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.823657     Document Type: Article

References (9)

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3. P. Black and T. Meng, "A 140 Mb/s 32-state radix-4 Viterbi decoder," IEEE J. Solid-State Circuits, vol. 27, pp. 1877-1885, Dec. 1992.
4. G. Fettweis and H. Meyr, "High rate Viterbi processor: A systolic array solution," IEEE J. Select. Areas Commun., vol. 8, pp. 1520-1534, Oct. 1990.
5. A. Yeung and J. Rabaey, "A 210 Mb/s radix-4 bit-level Viterbi decoder," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1995, pp. 88-89.
6. V. S. Gierenz, O. Weiss, T. G. Noll, I. Carew, J. Ashley, and R. Karabed, "A 550 Mb/s radix-4 bit-level pipelined 16-state 0.25-μm CMOS Viterbi decoder," in Proc. IEEE Int. Conf. Application-Specific Systems, Architectures, and Processors, 2000, pp. 195-201.
7. T. Gemmeke, M. Gansen, and T. G. Noll, "Implementation of scalable power and area efficient high-throughput Viterbi decoders," IEEE J. Solid-State Circuits, vol. 37, pp. 941-948, July 2002.
8. K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York: Wiley, 1999.
9. P. J. Black and T. H.-Y. Meng, "A 1-Gb/s, four-state, sliding block Viterbi decoder," IEEE J. Solid-State Circuits, vol. 32, pp. 797-805, June 1997.