Low-power bit-serial viterbi decoder for 3rd generation W-CDMA systems

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1999, Pages 589-592

  Suzuki, Hiroshi ^a   Chang, Yun Nan ^a   Parhi, Keshab K ^a  

^a JFE STEEL CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CODE DIVISION MULTIPLE ACCESS; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; DIGITAL ARITHMETIC;

ADD COMPARE SELECT UNITS; APPLICATION SPECIFIC MEMORY; BIT SERIAL ARITHMETIC; LOW POWER BIT SERIAL VITERBI DECODER;

DECODING;

EID: 0032597722     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (9)