SCOPUS 정보 검색 플랫폼

Volumn , Issue , 2002, Pages 343-348

Dynamic hardware plugins in an FPGA with partial Run-Time reconfiguration

Author keywords

FPGA; Hardware; Internet; IP; Modularity; Network; Packet; Partial RTR; Platf orm computing; Reconfiguration; Routing

Indexed keywords

FIELD PROGRAMMABLE PORT EXTENDERS; RUN-TIME RECONFIGURATION (RTR);

COMPUTER AIDED DESIGN; INTERNET; NETWORK PROTOCOLS; PACKET NETWORKS; ROUTERS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036054393 PISSN: 0738100X EISSN: None Source Type: Journal
DOI: 10.1109/DAC.2002.1012647 Document Type: Article

Times cited : (115)

References (19)

1
- 0000950606
- The roles of FPGAs in reprogrammable systems
- Apr
- (1998) Proceedings of the IEEE , vol.86 , pp. 615-638
- Hauck, S.¹

2
- 0032184323
- Protocol boosters: Applying programmability to network infrastructures
- (1998) IEEE Communications Magazine , vol.36 , Issue.10 , pp. 79-83
- Marcus, W.¹ Hadzic, I.² McAuley, A.³ Smith, J.⁴

3
- 84947929293
- Implementation approaches for reconfigurable logic applications
- W. Moore and W. Luk, eds., (Oxford, England), Springer-Verlag, Berlin, Aug
- (1995) Field-Programmable Logic and Applications (FPL’1995) , pp. 419-428
- Hutchings, B.L.¹ Wirthlin, M.J.²

4
- 84950148992
- Searching genetic databases on splash 2
- D. A. Buell and K. L. Pocek, eds., (Los Alamitos, CA), IEEE Computer Society Press
- (1993) IEEE Workshop on FPGAs for Custom Computing Machines , pp. 185-191
- Hoang, D.T.¹

5
- 0028738052
- PAM programming environments: Practice and experience
- D. A. Buell and K. L. Pocek, eds., (Los Alamitos, CA), IEEE Computer Society Press
- (1994) IEEE Workshop on FPGAs for Custom Computing Machines , pp. 133-138
- Bertin, P.¹ Touati, H.² Lagnese, E.³

7
- 0000672089
- An FPGA-based hardware accelerator for image processing
- W. Moore and W. Luk, eds., (Oxford, England)
- (1993) More FPGAs: Proceedings of the 1993 International workshop on field-programmable logic and applications , pp. 299-306
- Ross, D.¹ Vellacott, O.² Turner, M.³

8
- 0029490152
- Designing a partially reconfigured system
- Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing (J. Schewel, ed.), (Bellingham, WA), SPIE - The International Society for Optical Engineering
- (1995) Proc. SPIE , vol.2607 , pp. 210-220
- Hadley, J.D.¹ Hutchings, B.L.²

10
- 0003209270
- The architecture of a reconfigurable ATM switch (RECATS)
- Marília, SP, Brazil, Aug
- (2000) Workshop de Computção Reconfigurável
- Horta, E.L.¹ Kofuji, S.T.²

11
- 84962194782
- Dynamic Hardware Plugins (DHP): Exploiting reconfigurable hardware for high-performance programmable routers
- Anchorage, AK, Apr
- (2001) IEEE OPENARCH 2001: 4th IEEE Conference on Open Architectures and Network Programming
- Taylor, D.E.¹ Turner, J.S.² Lockwood, J.W.³

12
- 0033719066
- Field programmable port extender (FPX) for distributed routing and queuing
- Monterey, CA, USA, Feb
- (2000) ACM International Symposium on Field Programmable Gate Arrays (FPGA’2000) , pp. 137-144
- Lockwood, J.W.¹ Turner, J.S.² Taylor, D.E.³

13
- 0003200355
- Design of a flexible open platform for high performance active networks
- Champaign, IL
- (1999) Allerton Conference
- Choi, S.¹ Dehart, J.² Keller, R.³ Lockwood, J.W.⁴ Turner, J.⁵ Wolf, T.⁶

17
- 0035014657
- Reprogrammable network packet processing on the field programmable port extender (FPX)
- Monterey, CA, USA, Feb
- (2001) ACM International Symposium on Field Programmable Gate Arrays (FPGA’2001) , pp. 87-93
- Lockwood, J.W.¹ Naufel, N.² Turner, J.S.³ Taylor, D.E.⁴

18
- 84952905266
- Evolvable internet hardware platforms
- July
- (2001) NASA/DoD Workshop on Evolvable Hardware (EH’2001) , pp. 271-279
- Lockwood, J.W.¹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.