메뉴 건너뛰기




Volumn , Issue , 2003, Pages

Remote and partial reconfiguration of FPGAs: Tools and trends

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL DEVICES; DISTRIBUTED PARAMETER NETWORKS; RECONFIGURABLE HARDWARE;

EID: 84947230998     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2003.1213326     Document Type: Conference Paper
Times cited : (43)

References (26)
  • 1
    • 84893641728 scopus 로고    scopus 로고
    • A decade of reconfigurable computing: A visionary retrospective
    • Hartenstein, R. A decade of reconfigurable computing: A visionary retrospective. In: Design, Automation and Test in Europe, pp. 642-649, 2001.
    • (2001) Design, Automation and Test in Europe , pp. 642-649
    • Hartenstein, R.1
  • 4
    • 0030141850 scopus 로고    scopus 로고
    • Elsevier Microprocessors & Microsystems
    • Page, I. Reconfigurable processor architectures. Elsevier Microprocessors & Microsystems, v. 20, p. 185-196, 1996.
    • (1996) Reconfigurable Processor Architectures , vol.20 , pp. 185-196
    • Page, I.1
  • 5
    • 0030104367 scopus 로고    scopus 로고
    • Programmable active memories: Reconfigurable systems come of age
    • Vuillemin, J. E. ; et al. Programmable active memories: reconfigurable systems come of age. IEEE Transactions on VLSI Systems, vol 4(1), pp. 56-69, 1996.
    • (1996) IEEE Transactions on VLSI Systems , vol.4 , Issue.1 , pp. 56-69
    • Vuillemin, J.E.1
  • 6
    • 0027561268 scopus 로고
    • Processor reconfiguration through instruction-set metamorphosis
    • Athanas, P. ; Silverman, H. F. Processor reconfiguration through instruction-set metamorphosis. Computer, vol 26(3), pp. 11-18, 1993.
    • (1993) Computer , vol.26 , Issue.3 , pp. 11-18
    • Athanas, P.1    Silverman, H.F.2
  • 10
    • 0032686679 scopus 로고    scopus 로고
    • Static and dynamic configurable systems
    • Sanchez, E. ; et al. Static and dynamic configurable systems. IEEE Transactions on Computers, vol 48(6), pp. 556-564, 1999.
    • (1999) IEEE Transactions on Computers , vol.48 , Issue.6 , pp. 556-564
    • Sanchez, E.1
  • 13
    • 0034174174 scopus 로고    scopus 로고
    • The Garp architecture and C compiler
    • Callahan, T. J. ; Hauser, J. R. ; Wawrzynek, J. The Garp architecture and C compiler. Computer, vol. 33(4), pp. 62-69, 2000.
    • (2000) Computer , vol.33 , Issue.4 , pp. 62-69
    • Callahan, T.J.1    Hauser, J.R.2    Wawrzynek, J.3
  • 14
    • 0031236158 scopus 로고    scopus 로고
    • Baring it all to software: Raw machines
    • Waingold, E. ; et al. Baring it all to software: Raw machines. Computer, vol. 30(9), pp. 86-93, 1997.
    • (1997) Computer , vol.30 , Issue.9 , pp. 86-93
    • Waingold, E.1
  • 15
    • 0028738226 scopus 로고
    • DPGA-coupled microprocessors: Commodity ICs for the early 21st Century
    • DeHon, A. DPGA-coupled microprocessors: commodity ICs for the early 21st Century. In: FPGAS for Custom Computing Machines, pp. 31-39, 1994.
    • (1994) FPGAS for Custom Computing Machines , pp. 31-39
    • DeHon, A.1
  • 17
    • 0034174187 scopus 로고    scopus 로고
    • PipeRench: A reconfigurable architecture and compiler
    • Goldstein, S. C. ; et al. PipeRench: A reconfigurable architecture and compiler. Computer, vol 33(4), pp. 70-77, 2000.
    • (2000) Computer , vol.33 , Issue.4 , pp. 70-77
    • Goldstein, S.C.1
  • 18
    • 9544246714 scopus 로고    scopus 로고
    • Highly scalable dynamically reconfigurable systolic ring-architecture for DSP applications
    • Sassatelli, G. ; et al. Highly scalable dynamically reconfigurable systolic ring-architecture for DSP applications. In: DATE, pp. 553-558, 2002.
    • (2002) DATE , pp. 553-558
    • Sassatelli, G.1
  • 19
    • 84947574774 scopus 로고    scopus 로고
    • Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial
    • Villach, Austria
    • Caspi, E. ; et al. Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial. In: Field Programmable Logic and Applications (FPL'2000), Villach, Austria. pp 605-614. 2000
    • (2000) Field Programmable Logic and Applications (FPL'2000) , pp. 605-614
    • Caspi, E.1
  • 21
    • 84949795228 scopus 로고    scopus 로고
    • Automated extraction of run-time parameterisable cores from programmable device configurations
    • James-Roxby, P. ; Guccione, S. A. Automated extraction of run-time parameterisable cores from programmable device configurations. In: Field-Programmable Custom Computing Machines, pp. 153-161, 2000.
    • (2000) Field-Programmable Custom Computing Machines , pp. 153-161
    • James-Roxby, P.1    Guccione, S.A.2
  • 22
    • 79958290624 scopus 로고    scopus 로고
    • Sept.
    • XILINX. The Jbits 2. 8 SDK for Virtex. ftp://customer:xilinx@ftp. xilinx. com/download/JBits2-8. e xe (Sept. 2001).
    • (2001) The Jbits 2. 8 SDK for Virtex


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.