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Volumn , Issue , 2005, Pages 189-195

Flexible core reallocation for virtex II structures

Author keywords

Core reallocation; Partial run time reconfiguration; Virtex ii

Indexed keywords

SOFTWARE PROTOTYPING;

EID: 42649117134     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (4)

References (20)
  • 1
    • 34247343129 scopus 로고    scopus 로고
    • Dynamic Reconfiguration in Mobile Systems
    • Montpellier, France, ISBN 3-540-44108-5, pp, Sept
    • Gerard J. M. Smit et al., "Dynamic Reconfiguration in Mobile Systems", Proc. of the 12th Field-Programmable Logic and Applications (FPL'02), Montpellier, France, ISBN 3-540-44108-5, pp. 171-181. Sept 2002.
    • (2002) Proc. of the 12th Field-Programmable Logic and Applications (FPL'02) , pp. 171-181
    • Smit, G.J.M.1
  • 2
    • 60749103594 scopus 로고    scopus 로고
    • The Development of an Operating System for Reconfigurable Computing
    • Munich, Germany, pp, March
    • Grant Wigley, David Kearney, "The Development of an Operating System for Reconfigurable Computing", Proc. of Design, Automation and Test in Europe (DATE'03), Munich, Germany, pp. 290-295, March 2003
    • (2003) Proc. of Design, Automation and Test in Europe (DATE'03) , pp. 290-295
    • Wigley, G.1    Kearney, D.2
  • 5
    • 0036054393 scopus 로고    scopus 로고
    • Dynamic Hardware Plugins in an FPGA with Partial Run-Time Reconfiguration
    • New Orleans, Louisiana, USA, pp, June
    • Edson L. Horta, et al., "Dynamic Hardware Plugins in an FPGA with Partial Run-Time Reconfiguration", Proc. of the 39th Design Automation Conference (DAC'02), New Orleans, Louisiana, USA, pp. 343-348, June 2002.
    • (2002) Proc. of the 39th Design Automation Conference (DAC'02) , pp. 343-348
    • Horta, E.L.1
  • 6
    • 60749120868 scopus 로고    scopus 로고
    • Davin Lim, Mike Peattie, Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations, Xilinx, XAPP290 (vl.0), May 2002.
    • Davin Lim, Mike Peattie, "Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations", Xilinx, XAPP290 (vl.0), May 2002.
  • 7
    • 34548343396 scopus 로고    scopus 로고
    • Ryan J., Scott J. Harper, Peter M. Athanas, A versatile Framework for FPGAs Field Updates: An Application of Partial Self-Reconfiguration, Proc. of the 14th IEEE Intl. Workshop on Rapid System Prototyping (RSP'03), San Diego, CA, USA, pp. 117-123, June 2003.
    • Ryan J., Scott J. Harper, Peter M. Athanas, "A versatile Framework for FPGAs Field Updates: An Application of Partial Self-Reconfiguration", Proc. of the 14th IEEE Intl. Workshop on Rapid System Prototyping (RSP'03), San Diego, CA, USA, pp. 117-123, June 2003.
  • 8
    • 84947926905 scopus 로고    scopus 로고
    • A Runtime Environment for Reconfigurable Hardware Operating System
    • Antwerp, Belgium, ISBN 3-540-22989-2, pp, Sept
    • Herbert Walder, Marko Platzner, "A Runtime Environment for Reconfigurable Hardware Operating System", Proc. of the 14th Field-Programmable Logic and Applications (FPL'04), Antwerp, Belgium, ISBN 3-540-22989-2, pp. 831-835, Sept 2004.
    • (2004) Proc. of the 14th Field-Programmable Logic and Applications (FPL'04) , pp. 831-835
    • Walder, H.1    Platzner, M.2
  • 10
    • 84947928278 scopus 로고    scopus 로고
    • Edson L. Horta, John W. Lockwood, Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs, in Proc. of the 14th Field-Programmable Logic and Applications (FPL'04), Antwerp, Belgium, ISBN 3-540-22989-2, pp. 975-979, Sep 2004.
    • Edson L. Horta, John W. Lockwood, "Automated Method to Generate" Bitstream Intellectual Property Cores for Virtex FPGAs", in Proc. of the 14th Field-Programmable Logic and Applications" (FPL'04), Antwerp, Belgium, ISBN 3-540-22989-2, pp. 975-979, Sep 2004.
  • 12
    • 79955155845 scopus 로고    scopus 로고
    • Matthias Dyer, Chirstian Plessl, Marko Platzner Partially Reconfigurable Cores for Xilinx Virtex, in Proc. of Field-Programmable Logic and Applications (FPL'02), Montpellier, France, ISBN 3-540-44108-5, pp 292-301, September 2002.
    • Matthias Dyer, Chirstian Plessl, Marko Platzner "Partially Reconfigurable Cores for Xilinx Virtex", in Proc. of Field-Programmable Logic and Applications" (FPL'02), Montpellier, France, ISBN 3-540-44108-5, pp 292-301, September 2002.
  • 14
    • 84966573925 scopus 로고    scopus 로고
    • JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGA
    • Florida, USA, pp, April
    • Anup Kumar Raghavam, Peter Suttom, "JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGA", Proc. of Parallel and Distributed Processing Symposium (IPDPS'02), Florida, USA, pp. 155-160, April 2002.
    • (2002) Proc. of Parallel and Distributed Processing Symposium (IPDPS'02) , pp. 155-160
    • Kumar Raghavam, A.1    Suttom, P.2
  • 16
    • 60749111457 scopus 로고    scopus 로고
    • http://www.arl.wustl.edu/arl/projects/fpx/parbit/
  • 17
    • 60749122301 scopus 로고    scopus 로고
    • Xilinx inc
    • Xilinx inc., online http:\\xilinx.com\products\jbits.
    • online
  • 20
    • 60749091451 scopus 로고    scopus 로고
    • http://projects.archetypon.com/enamorado/


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.