A novel dynamic threshold operation using electrically induced junction MOSFET in the deep sub-micrometer CMOS regime

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 499-503

  Dixit, A ^a,b   Rao, V R ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b IMEC   (Belgium)

Author keywords

Circuit simulation; Degradation; MOSFET circuits; Parasitic capacitance; Power MOSFET; Power supplies; Substrates; Threshold voltage; Ultra large scale integration; Very large scale integration

Indexed keywords

CAPACITANCE; CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; DEGRADATION; DESIGN; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; LOW POWER ELECTRONICS; MOSFET DEVICES; SUBSTRATES; SYSTEMS ANALYSIS; THRESHOLD VOLTAGE; VLSI CIRCUITS;

DEEP-SUB MICROMETERS; DYNAMIC THRESHOLD MOSFET; HIGH-SPEED OPERATION; MOSFET CIRCUITS; PARASITIC CAPACITANCE; POWER MOSFET; POWER SUPPLY; TRANSIENT SIMULATION;

ULSI CIRCUITS;

EID: 41749122053     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183183     Document Type: Conference Paper

References (9)

1. F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, "Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-low Voltage VLSI", IEEE Trans. Electron Devices, vol. 44 (3), March 1997, pp. 414-421.
2. F. Assaderaghi et al, "Channel, Profile Optimization and Device Design for Low Power High-Performance Dynamic Threshold MOSFET", pp. 113-116, IEDM, 1997.
3. Anne-Johan Annema, "Low-Power Bandgap References Featuring DTMOST's", IEEE Journal of Solid State Circuits, vol.34 (7), pp.949-955, July 1999.
4. H. Noda, F. Murai, and S. Kimura, "Short Channel Characteristics of Si MOSFET With Extremely Shallow Source and Drain Regions Formed by Inversion Layers", IEEE Trans. on Electron Devices, 41 (10), 1994, pp 1831.
5. S. Tiwari, J. J. Welser, and P. M. Solomon, "Straddle-Gate Transistor: Changing MOSFET Channel Length Between Off- and On-State Towards Achieving Tunneling-Defined Limit of Field-Effect," IEDM 98, pp. 737-740, 1998.
6. A. Dixit, R. O. Dusane, and V. Ramgopal Rao, "Electrically Induced Junction MOSFET for High Performance Sub-50nm CMOS Technology", The Proceedings of The Materials Research Society (MRS)", San Francisco USA, April 2002.
7. ISE-TCAD User's Manual-Release 6(1, 3, 4, 5), Integrated Systems Engineering AG, Technoparkstrasse 1, CH-8005 Zurich / Switzerland.
8. Y. A. El-Mansy, "VLSI Symposium and Silicon Technology: a twenty year perspective", Symposium on VLSI Technology Digest of Technical Papers, 2000, pp 2.
9. S. Song, J. H. Yi, W. S. Kim, J. S. Lee, K. Fujihara, H. K. Kang, J. T. Moon, and M. Y. Lee, "CMOS device scaling beyond 100nm", The International Electron Devices Meeting IEDM 00, 2000, pp 235.