Efficient RTL coverage metric for functional test selection

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2007, Pages 318-324

  Kang, Jian ^a   Seth, Sharad C ^a   Gangaram, Vijay ^b  

^a UNIVERSITY OF NEBRASKA LINCOLN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL EFFICIENCY; FAILURE ANALYSIS; FUNCTIONAL ANALYSIS; MICROPROCESSOR CHIPS; TRANSFER FUNCTIONS;

COMPUTATIONAL COSTS; FUNCTIONAL TEST SELECTION; TESTABILITY ANALYSIS; TRANSITION FAULT-COVERAGE METRIC (TRIO);

ELECTRONIC EQUIPMENT TESTING;

EID: 37549050573     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2007.30     Document Type: Conference Paper

References (21)

1. P. Parvathala, K. Maneparambil, and W. Lindsay, "FRITS - a microprocessor functional BIST method," in International Test Conference, 2002.
2. F. Fummi, G. Pravadelli, and F. Toto, "Coverage of formal properties based on a high-level fault model and functional ATPG," in European Test Symposium, 2005.
3. M. B. Santos, F. M. Goncalves, I. C. Teixeira, and J. P. Teixeira, "RTL-based functional test generation for high defects coverage in digital SOCs," in European Test Workshop, 2000.
4. P. Maxwell, I. Hartanto, and L. Bentz, "Comparing functional and structural tests," in International Test Conference, 2000.
5. P. Nigh, W. Needham, K. Butler, P. Maxwell, and R. Aitken, "An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing," in VLSI Test Symposium, 1997.
6. C. Chang Hyun and J. R. Armstrong, "B-algorithm: a behavioral test generation algorithm," in International Test Conference, 1994.
7. Y. V. Hoskote, D. Moundanos, and J. A. Abraham, "Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors," in International Conference on Computer Design, 1995.
8. G. Al Hayek and C. Robach, "From specification validation to hardware testing: a unified method," in International Test Conference, 1996.
9. M. Karunaratne, A. Sagahayroon, and S. Prodhuturi, "RTL fault modeling," in Midwest Symposium on Circuits and Systems, 2005, Vol. 2.
10. F. Fallah, S. Devadas, and K. Kuetzer, "OCCOM: efficient computation of observability-based code coverage metrics for functional verification," in Design Automation Conference, 1998.
11. W. Mao and R. K. Gulati, "Improving gate level fault coverage by RTL fault grading," in International Test Conference, 1996.
12. P. A. Thaker, V. D. Agrawal, and M. E. Zaghloul, "Validation vector grade (VVG): a new coverage metric for validation and test," in Proceedings 17th IEEE VLSI Test Symposium, Dana Point, CA, USA, 1999.
13. F. Fummi, C. Marconcini, and G. Pravadelli, "Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?," in Ninth IEEE European Test Symposium, 2004.
14. M. B. Santos, F. M. Goncalves, I. C. Teixeira, and J. P. Teixeira, "Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level," in International Test Conference, 2001.
15. C. J. Stoucny, R. Davies, P. McKernan, and T. Truong, "Alpha 21164 manufacturing test development and coverage analysis," Design & Test of Computers, IEEE, vol. 15, 1998.
16. S. Park, L. Chen, P. Parvathala, S. Paul, and I. Pomeranz, "A functional coverage metric for estimating the gate-level fault coverage of functional tests," in International Test Conference, 2006.
17. V. Gangaram, D. Bhan, and J. K. Caldwell, "Functional Test Selection Using Dynamic Untestability Analysis," in International Workshop on Microprocessor Test and Verification, 2006.
18. D. Drako and P. Cohen, "HDL Verification Coverage," in Integrated System Design, 1998.
19. I. Pomeranz, S. M. Reddy, and J. H. Patel, "On double transition faults as a delay fault model," in Great Lakes Symposium on VLSI, 1996.
20. J. Yi and J. P. Hayes, "The Coupling Model for Function and Delay Faults," Journal of Electronic Testing: Theory and Applications, vol. 21, 2005.
21. L. Xijiang, I. Pomeranz, and S. M. Reddy, "MIX: a test generation system for synchronous sequential circuits," in International Conference on VLSI Design, 1998.