Implicit functionality and multiple branch coverage (IFMB): A testability metric for RT-level

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 377-385

  Santos, M B ^a   Goncalves F M ^a   Teixeira, I C ^a   Teixeira, J P ^a  

^a INESC ID   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; LOGIC CIRCUITS; MATHEMATICAL MODELS;

REGISTER-TRANSFER LEVEL (RTL) TESTABILITY;

INTEGRATED CIRCUIT TESTING;

EID: 0035683984     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

1. OCCOM: Efficient computation of observability-based code coverage metrics for functional verification
2. Validation vector grade (VVG): A new coverage metric for validation and test
3. Register-transfer level fault modeling and test evaluation techniques for VLSI circuits
4. From specification validation to hardware testing: A unified method
5. Behavioral fault modeling in a VHDL synthesis environment
6. Implicit test generation for behavioral VHDL models
7. Behavioral fault simulation in VHDL
8. Using target faults to detect non-target defects
9. RTL-based functional test generation for high defect coverage in digital SOCs
10. Defect-oriented verilog fault simulation of SoC macros using a stratified fault sampling technique
11. Correlating testability with fault detection
12. RTL guided random-pattern-resistant fault detection and low energy BIST