Improving gate level fault coverage by RTL fault grading

IEEE International Test Conference (TC)

Volumn , Issue , 1996, Pages 150-159

  Mao, Weiwei ^a   Gulati, Ravi K ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; LOGIC CIRCUITS; LOGIC DESIGN; LOGIC GATES;

FAULT DETECTION SIMULATOR; GATE LEVEL FAULT COVERAGE; RESISTOR TRANSISTOR LOGIC (RTL);

INTEGRATED CIRCUIT TESTING;

EID: 0030388487     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)