A functional coverage metric for estimating the gate-level fault coverage of functional tests

Proceedings - International Test Conference

Volumn , Issue , 2006, Pages

  Park, Sungchul ^a   Chen, Li ^b   Parvathala, Praveen K ^b   Patil, Srinivas ^b   Pomeranz, Irith ^a  

^a Purdue University

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; LOGIC GATES; MICROPROCESSOR CHIPS; OBJECT RECOGNITION; SOFTWARE ARCHITECTURE; SOFTWARE TESTING;

DEGREE OF CORRELATION; FUNCTIONAL TESTS; GATE-LEVEL FAULT COVERAGE;

FAULT TOLERANCE;

EID: 39749103500     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2006.297674     Document Type: Conference Paper

References (16)