On double transition faults as a delay fault model

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1996, Pages 282-287

  Pomeranz, I ^a   Reddy, S M ^a   Patel, J H ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DELAY LINES; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; TESTING;

DELAY FAULTS;

ELECTRIC FAULT LOCATION;

EID: 0029720309     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)