Alpha 21164 manufacturing test development and coverage analysis

IEEE Design and Test of Computers

Volumn 15, Issue 3, 1998, Pages 98-104

  Stolicny, Carol J ^a,b,c   Davies, Richard ^a,c,d,e   Mckernan, Pamela ^a,f   Truong, Tuyen ^a,f,g  

^a HEWLETT PACKARD COMPANY   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^c IEEE   (United States)

^d UNIVERSITY OF CINCINNATI   (United States)

^e NORTHEASTERN UNIVERSITY   (United States)

^f PENNSYLVANIA STATE UNIVERSITY   (United States)

^g Alpha Prod and Test Eng Group

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DISTRIBUTED COMPUTER SYSTEMS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

DESIGN FOR TEST (DFT) TECHNIQUES;

MICROPROCESSOR CHIPS;

EID: 0032114986     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.706040     Document Type: Article

References (7)

1. D.K. Bhavsar and J.H. Edmondson, "Alpha 21164 Testability Strategy," IEEE Design & Test of Computers, Jan.-Mar. 1997, pp. 25-53.
2. P.C. Maxwell et al., "The Effect of Different Test Sets on Quality Level Prediction: When is 80% Better than 90%?" IEEE Int'l Test Conf., IEEE Computer Society Press, Los Alamitos, Calif., Oct. 1991, pp. 358-364.
3. M. Kantrowitz and L. M. Noack, "I'm Done Simulating; Now What? Verification Coverage Analysis and Correctness Checking of the DEC Chip 21164 Alpha Microprocessor," Proc. 33rd Design Automation Conf., ACM, New York, June 1996, pp. 325-330.
4. M. Kantrowitz and L. M. Noack, "Functional Verification of a Multiple-Issue, Pipelined, Superscalar, Alpha Processor - the Alpha 21164 CPU Chip," Digital Tech. J., Vol 7, No. 1, 1995, pp. 136-144.
5. V.D. Agrawal, "Sampling Techniques for Determining Fault Coverage in LSI Circuits," J. Digital Systems, Vol. 5, No. 3, 1981, pp. 189-202.
6. C.F. Hawkins et al., "Defect Classes - An Overdue Paradigm for CMOS IC Testing," IEEE Int'l Test Conf., IEEE CS Press, Oct. 1994, pp. 413-425.
7. G.W. Papadeas and D. Gauthier, "An On-Line Data Collection System for VLSI Devices at Wafer Probe and Final Test," IEEE Int'l Test Conf., IEEE CS Press, Oct. 1994, pp. 771-780.