The coupling model for function and delay faults

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 21, Issue 6, 2005, Pages 631-649

  Yi, Joonhwan ^a   Hayes, John P ^b,c,d,e  

^a SAMSUNG Electronics   (South Korea)

^b UNIVERSITY OF MICHIGAN   (United States)

^c IEEE   (United States)

^d ACM   (United States)

^e ACM ^*  (United States)

Author keywords

Delay faults; Fault modeling; Functional faults; Test generation

Indexed keywords

DELAY FAULTS; FAULT MODELING; FUNCTIONAL FAULTS; TEST GENERATION;

COUPLED CIRCUITS; DELAY CIRCUITS; FORMAL LOGIC; MATHEMATICAL MODELS; ROBUSTNESS (CONTROL SYSTEMS);

ELECTRIC FAULT CURRENTS;

EID: 27844556917     PISSN: 09238174     EISSN: 15730727     Source Type: Journal    
DOI: 10.1007/s10836-005-3476-y     Document Type: Conference Paper

References (25)

1. S.B. Akers, "Universal Test Sets for Logic Networks," IEEE Trans. on Computers, vol. C-22, no. 9, pp. 835-839, 1973.
2. H. Al-Asaad, J.P. Hayes, and B.T. Murray, "Scalable Test Generators for High-Speed Datapath Circuits," Journal of Electronic Testing, vol. 12, pp. 111-125, 1998.
3. M.J. Batek and J.P. Hayes, "Test-Set Preserving Logic Transformations," in Proc. Design Automation Conf., pp. 454-4-58, 1992.
4. R. Betancourt, "Derivation of Minimum Test Sets for Unate Logic Circuits," IEEE Trans. on Computers, vol. C-20, no. 11, pp. 1264-1269, 1971.
5. K.-T. Cheng, A. Krstic, and H-C Chen, "Generation of High Quality Tests for Robustly Untestable Path Delay Faults," IEEE Trans. on Computers, vol. 45, no. 12, pp. 1379-1392, 1996.
6. K. De, "Test Methodology for Embedded Cores which Protects Intellectual Property," in Proc. VLSI Test Symposium, 1997, pp. 2-9
7. B.I. Dervisoglu, "A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers," in Proc. Design Automation Conference, pp. 53-58, 2001.
8. S. Devadas and K. Keutzer, "Synthesis of Robust Delay-Fault-Testable Circuits: Theory," IEEE Trans. on CAD, vol. 11, no. 1, pp. 87-101, 1992.
9. M. Gharaybeh, M.L. Bushnell, and V.D. Agrawal. "Classification and Test Generation for Path-Delay Faults Using Single Stuck-at Fault Tests," Journal of Electronic Testing, vol. 11, pp. 55-67, 1997.
10. P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Trans. on Computers, vol. C-30, no. 3, pp. 215-222, 1981.
11. J.P. Hayes, "On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests," IEEE Trans. on Computers, vol. C-20, no. 12, pp. 1506-1513, 1971.
12. W. Ke and P.R. Menon, "Synthesis of Delay-Verifiable Combinational Circuits," IEEE Trans. on Computers, vol. 44, no. 2, 1995.
13. H. Kim and J.P. Hayes, "Delay Fault Testing of Designs with Embedded IP Cores," in Proc. VLSI Test Symposium, 1999, pp. 160-167.
14. H. Kim and J.P. Hayes, "Realization-Independent ATPG for Designs with Unimplemented Blocks," IEEE Trans. on CAD, vol. 20, no. 2, pp. 290-306, 2001.
15. T. Larrabee, "Efficient Generation of Test Patterns Using Boolean Difference," in Proc. International Test Conf., pp. 795-801, 1989.
16. H.K. Lee and D.S. Ha, "On the Generation of Test Patterns for Combinational Circuits," Tech. Report 12-93, EE Dept., Virginia Polytechnic Institute and State University, 1993.
17. C.J. Lin and S.M. Reddy, "On Delay Fault Testing in Logic Circuits," IEEE Trans. on CAD, vol. CAD-6, no. 5, pp. 694-703, 1987.
18. I. Pomeranz and S.M. Reddy, "On Testing Delay Faults in Macro-Based Combinational Circuits," in Proc. International Conf. on CAD, pp. 332-339, 1994.
19. I. Pomeranz and S.M. Reddy, "Functional Test Generation for Delay Faults in Combinational Circuits," in Proc. International Conf. on CAD, pp. 687-694, 1995.
20. M. Psarakis, D. Gizopoulos, and A. Paschalis, "Test Generation and Fault Simulation for Cell Fault Model Using Stuck-at Fault Model Based Test Tools," Journal of Electronic Testing, vol. 13, pp. 315-319, 1998.
21. M. Psarakis et al., "Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays," IEEE Trans. on Computers, vol. 49, no. 10, pp. 1083-1099, 2000.
22. J. Rajski and J. Vasudevamurthy, "The Testability-Preserving Concurrent Decomposition and Factorization of Boolean Expressions," IEEE Trans. on CAD, vol. 11, no. 6, pp. 778-793, 1992.
23. G.L. Smith, "Model for Delay Faults Based Upon Paths," in Proc. International Test Conf., pp. 342-349, 1985.
24. U. Sparmann, H. Muller, and S.M. Reddy, "Universal Delay Test Sets for Path Delay Faults," IEEE Trans. on VLSI Systems, vol. 7, no. 2, pp. 156-166, 1999.
25. J. Yi, "High-Level Function and Delay Testing for Digital Circuits," Ph.D Thesis, University of Michigan, 2002.