RTL fault modeling

Midwest Symposium on Circuits and Systems

Volumn 2005, Issue , 2005, Pages 1717-1720

  Karunaratne, M ^a   Sagahyroon, A ^b   Prodhuturi, S ^c  

^a UNIVERSITY OF PITTSBURGH   (United States)

^b AMERICAN UNIVERSITY OF SHARJAH   (United Arab Emirates)

^c CALIFORNIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL CIRCUITS; MATHEMATICAL MODELS;

DESIGN METHODOLOGY; FAULT SIMULATION; REGISTER TRANSFER (RT); RTL FAULT MODELING;

ELECTRIC FAULT CURRENTS;

EID: 33847109477     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2005.1594451     Document Type: Conference Paper

References (8)

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2. Ronald J. Hayne and Barry W. Johnson, "Behavioral Fault Modeling in a VHDL Synthesis Environment", IEEE VLSI Test symposium, 1999 1999
3. S. Devavdas, A. Ghosh, K. Keutzer "An Observability-Based Code Coverage Metric for Functional Simulation" Proceedings of IEEE/ACM International Conference on Computer Aided Design, 1996
4. F.Corno, G. Cumani, M. Sonza Reorda, G. Squillero, "An RT-level Fault Model with High Gate Level Correlation" Proceedings of the IEEE International High-Level Design Validation Test Workshop, 2000
5. Weiwei Mao, Ravi K. Gulati, "Improving Gate Level Fault Coverage by RTL Fault Grading", Proceedings of the International Test Conference, IEEE, 1996
6. Miron Abromovici, Melvin A. Breuer, Arthur D. Friedman, "Digital Systems Testing and Testable Design" Computer Science Press, 1990
7. URL: www.v-cube.com
8. Fatemah Khaani and Zainalabedin Navabi, "VHDL Structural Models for the Implementation of Path Sensitization Test Generation" ICEHDL WMC 1995