A self-consistent substrate thermal profile estimation technique for nanoscale ICs - Part I: Electrothermal couplings and full-chip package thermal model

IEEE Transactions on Electron Devices

Volumn 54, Issue 12, 2007, Pages 3342-3350

  Lin, Sheng Chih ^a   Chrysler, Greg ^b   Mahajan, Ravi ^b   De, Vivek K ^c   Banerjee, Kaustav ^a  

^a University of California   (United States)

^b INTEL CORPORATION   (United States)

^c INTEL RESEARCH   (United States)

Author keywords

Electrothermal couplings; Integrated circuits; Integrated circuits (ICs); Leakage; Leakage currents; Package; Performance; Performance evaluation; Power; Thermal analysis; Thermal management

Indexed keywords

ELECTRIC POTENTIAL; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; SEMICONDUCTING SILICON; SEMICONDUCTOR JUNCTIONS; TEMPERATURE CONTROL; THERMOANALYSIS;

ELECTROTHERMAL COUPLINGS; FULL-CHIP PACKAGE; NANOSCALE INTEGRATED CIRCUITS; SILICON JUNCTION;

ELECTRONICS PACKAGING;

EID: 36849089005     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.909039     Document Type: Article

References (33)

1. G. E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, no. 8, pp. 114-117, Apr. 1965.
2. G. E. Moore, "Progress in digital integrated electronics," in IEDM Tech. Dig., 1975, pp. 11-13.
3. R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LeBlanc, "Design of ion-implanted MOSFET's with very small physical dimensions," IEEE J. Solid-State Circuits, vol. SSC-9, no. 5, pp. 256-268, Oct. 1974.
4. S. Borkar, "Design challenges of technology scaling," IEEE Micro vol. 19, no. 4, pp. 23-29, Jul./Aug. 1999.
5. P. P. Gelsinger, "Microprocessors for the new millennium: Challenges, opportunities, and new frontiers," in Proc. IEEE Int. Solid-State Circuits Conf., 2001, pp. 22-25.
6. V. De and S. Borkar, "Technology and design challenges for low power and high performance," in Proc. IEEE Int. Symp. Low Power Electron. Des., 1999, pp. 163-168.
7. International Technology Roadmap for Semiconductors (ITRS). [Online]. Available: http://www.itrs.net
8. K. Banerjee, S.-C. Lin, and N. Srivastava, "Electrothermal engineering in the nanometer era: From devices and interconnects to circuits and systems," in Proc. 11th Asia South Pac. Des. Autom. Conf., 2006, pp. 223-230.
9. P. Tadayon, "Thermal challenges during microprocessor testing," Intel Technol. J., vol. 4, no. 3, pp. 1-8, 2000. 3rd quarter.
10. R. Viswanath, V. Wakharkar, A. Watwe, and V. Lebonheur, "Thermal performance challenges from silicon to system," Intel Technol. J. vol. 4, no. 3, pp. 1-16, 2000. 3rd quarter.
11. R. S. Prasher, J.-Y. Chang, I. Sauciuc, S. Narasimhan, D. Chau, G. Chrysler, A. Myers, S. Prstic, and C. Hu, "Nano and micro technology-based next-generation package-level cooling solutions," Intel Technol. J., vol. 9, no. 4, pp. 285-296, 2005. 4th quarter.
12. K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu, "The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal," in IEDM Tech. Dig., 1996, pp. 65-68.
13. S. Im and K. Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs," in IEDM Tech. Dig., 2000, pp. 727-730.
14. K. Banerjee and A. Mehrotra, "Global (interconnect) warnimg," IEEE Circuits Devices Mag., vol. 17, no. 5, pp. 16-32, Sep. 2001.
15. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and microarchitecture," in Proc. Des. Autom. Conf., 2003, pp. 338-342.
16. S. Narendra, V. De, S. Borkar, D. Antoniadis, and A. Chandrakasan, "Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS," in Proc. Int. Symp. Low Power Electron. Des., 2002, pp. 19-23.
17. P. Gelsinger, in Proc. 41st Des. Autom. Conf. Keynote, 2004.
18. Y.-S. Lin, C.-C. Wu, C.-S. Chang, R.-P. Yang, W.-M. Chen, J.-J. Liaw, and C. H. Diaz, "Leakage scaling in deep submicron CMOS for SoC," IEEE Trans. Electron Devices, vol. 49, no. 6, pp. 1034-1041, Jun. 2002.
19. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.
20. K. Banerjee, S.-C. Lin, A. Keshavarzi, S. Narendra, and V. De, "A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management," in IEDM Tech. Dig., 2003, pp. 36.7.1-36.7.4.
21. S.-C. Lin, G. Chrysler, R. Mahajan, V. K. De, and K. Banerjee, "A self-consistent substrate thermal profile estimation technique for nanoscale ICs - Part II: Implementation and implications for power estimation and thermal management," IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3351-3360, Dec. 2007.
22. A. Chatterjee, M. Nandakumar, and I. C. Chen, "An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits," in Proc. IEEE Int. Symp. Low Power Electron. Des., 1996, pp. 145-150.
23. K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnects in nanometer designs," IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 2001-2007, Nov. 2002.
24. P. M. Zeitzoff, "MOSFET scaling trends and challenges through the end of the roadmap," in Proc. Custom Integr. Circuits Conf., 2004, pp. 233-240.
25. S.-C. Lin, A. Basu, A. Keshavarzi, V. De, A. Mehrotra, and K. Banerjee, "Impact of off-state leakage current on electromigration design rules for nanometer scale CMOS technologies," in Proc. IEEE Int. Reliab. Phys. Symp., 2004, pp. 74-78.
26. A. Basu, S.-C. Lin, V. Wason, A. Mehrotra, and K. Banerjee, "Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era," in Proc. ACM Des. Autom. Conf., 2004, pp. 884-887.
27. S.-C. Lin, N. Srivastava, and K. Banerjee, "A thermally-aware methodology for design-specific optimization of supply and threshold voltages in nanometer scale ICs," in Proc. Int. Conf. Comput. Des. 2005, pp. 411-416.
28. J. Adam, C.-S. Chang, J. J. Stankus, M. K. Iyer, and W. T. Chen, "Addressing packaging challenges," IEEE Circuits Devices Mag., vol. 18, no. 4, pp. 40-49, Jul. 2002.
29. R. Mahajan, R. Nair, V. Wakharkar, J. Swan, J. Tang, and G. Vandentop, "Emerging directions for packaging technologies," Intel Technol. J. vol. 6, no. 2, pp. 62-75, 2002. 2nd quarter.
30. S. Im, N. Srivastava, K. Banerjee, and K. E. Goodson, "Scaling analysis of multilevel interconnect temperatures for high-performance ICs," IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2710-2719, Dec. 2005.
31. R. D. Cess, "The effect of radiation upon forced-convection heat transfer," Appl. Sci. Res., vol. 10, no. 1, pp. 430-438, Jan. 1961.
32. M.N. Özişik, Boundary Value Problems of Heat Conduction. New York: Dover, 2002.
33. BSIM4 MOSFET Model by the BSIM Research Group in the Department of EECS, UC-Berkeley. [Online]. Available: http://www.device. eecs.berkeley.edu/-bsim3/bsim4_intro.html