Impact of off-state leakage current on electromigration design rules for nanometer scale CMOS technologies

IEEE International Reliability Physics Symposium Proceedings

Volumn 2004-January, Issue January, 2004, Pages 74-78

  Lin, Sheng Chih ^a   Basu, Anirban ^a   Keshavarzi, Ali ^b   De, Vivek ^b   Mehrotra, Amit ^c   Banerjee, Kaustav ^a  

^a Santa Barbara   (United States)

^b INTEL RESEARCH   (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTROMIGRATION; INTEGRATED CIRCUIT DESIGN; LEAKAGE CURRENTS; MICROSTRIP LINES;

COMPREHENSIVE DESIGNS; DESIGN RULES; INTERCONNECT METALS; JUNCTION TEMPERATURES; NANOMETER-SCALE CMOS; OFF-STATE LEAKAGE CURRENT; SIGNAL LINES; TEMPERATURE RISE;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 33646211108     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2004.1315304     Document Type: Conference Paper

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