Conventional technological boosters for injection velocity in ultra thin body MOSFETs

IEEE Transactions on Nanotechnology

Volumn 6, Issue 6, 2007, Pages 613-622

  Ferner, M ^b,c   Clerc, R ^b   Lucci, L ^a,d   Rafhay, Q ^b   Pananakakis, G ^b   Ghibaudo, G ^a,b   Boeuf, F ^e   Skotnicki, T ^a,e  

^a IEEE

^b Institute of Microelectronic Electromagnetism and Photonics   (France)

^c STANFORD UNIVERSITY   (United States)

^d UNIVERSITY OF UDINE   (Italy)

^e STMICROELECTRONICS   (France)

Author keywords

Ballistic transport; BOX thickness; High k; Injection velocity; Subband engineering; Ultra thin body devices

Indexed keywords

BALLISTIC TRANSPORTS; BOX THICKNESS; INJECTION VELOCITY; SILICON THICKNESS THINNING; SUBBAND ENGINEERING; ULTRA THIN BODY DEVICES;

ELECTRIC EXCITERS; SEMICONDUCTING GERMANIUM; SILICON; VELOCITY CONTROL;

MOSFET DEVICES;

EID: 36348943020     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2007.907846     Document Type: Article

References (30)

1. International Technology Roadmap of Semiconductors, [Online], http://www.itrs.net/Common/2005ITRS/Home2005.htm
2. K. Natori, "Ballistic metal-oxide-semiconductor field effect transistor", J. Appl. Phys., vol. 76 (8), pp. 4879-1890, October 1994
3. M. Lundstrom, "Essential Physics of Carrier Transport in Nanoscale MOSFETs", IEEE Trans. Electron Devices, vol. 49, pp. 133-141, January 2002
4. L. Lucci, P. Palestri, D. Esseni, L. Selmi, "Multi-subband Monte Carlo modeling of nano-MOSFETs with strong vertical quantization and electron gas degeneration," in Proc IEDM 2005, pp.631
5. S. Takagi, "Re-examination of Subband Structure engineering in UltraShort Channel MOSFETs under Ballistic Carrier Transport" in Proc VLSI 2003
6. S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, S. Nakaharai, T. Numata, J. Koga, K. Uchida, "Sub-band Structure engineering for Advanced CMOS channels", Solid-State electronics, vol. 49, pp. 684-694, 2005
7. F. Assad, Z. Ren, D. Vasileska, S. Datta, M. Lundstrom, "On the Performance Limits for Si MOSFET's : A theoretical Study", IEEE Trans. Electron Devices, vol. 47, pp. 232-240, January 2000
8. S. E. Laux, "Optimum Crystallographic Alignment for Si n-Channel Ballistic DGFETs", IEEE Electron Device Letters, vol. 26(9), pp. 679-681, September 2005
9. T. Low, Y. T. Hou, M. F. Li, C. Zhu, A. Chin, G. Samudra, L. Chan, D. L. Kwong, "Investigation of Performance Limits of Germanium DoubleGated MOSFETs", in Proc IEDM 2003, pp.691
10. A. Pethe, T. Krishnamohan, D. Kim, S. Oh, H. S. P. wong, Y. Nishi, K. C. Saraswat, "Investigation of the performance limits of HI-V DoubleGate n-MOSFETs", in Proc IEDM 2005, pp.605
11. C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, F. Boeuf, "Requirements for Ultra-Thin-Film devices and New Materials for the CMOS Roadmap", Solid-State Electronics, vol. 48, pp. 961-967, 2004.
12. 1/2(η) used to describe electron density in a semiconductor", Solid-State electronics, vol. 25, pp. 1067-1076, 1982
13. A. Rahman, J. Guo,S. Datta and M. Lundstrom , "Theory of ballistic nanotransistors" IEEE Trans. Electron Devices, vol. 50, pp. 1853-1864, September 2003
14. P. Palestri, E. Esseni, S. Eminente, C. Fiegna, E. Sangiorgi, L. Selmi, "Understanding Quasi-Ballistic Transport in Nano-MOSFETs: Part Iscattering in the Channel and in the Drain", IEEE Trans. Electron Devices, vol. 52, pp. 2727-2735, December 2005
15. K. Banoo, M. Lundstrom, "Electron Transport in a Model Si transistor", Solid-State electronics, vol. 44, pp. 1689-1695, 2000
16. M. Lundstrom, "Device Physics at the Scaling Limit: What Matters?", in Proc IEDM 2003, pp.789.
17. S. Eminente, D. Esseni, P. Palestri, C. Fiegna, L. Selmi and E. Sangiorgi, "Enhanced Ballisticity in nano-MOSFETs along the ITRS Roadmap: A Monte Carlo Study" in Proc IEDM 2004, pp.609
18. S. Eminente, D. Esseni, P. Palestri, C. Fiegna, L. Selmi and E. Sangiorgi, "Understanding Quasi-Ballistic Transport in NanoMOSFETs: Part II-Technology Scaling along the ITRS", IEEE Trans. Electron Devices, vol. 52, pp. 2736-2743, December 2005
19. A. Rahman, M. Lundstrom, "A compact Scattering Model for the Nanoscale Double-Gate MOSFET", IEEE Trans. Electron Devices, vol. 49, pp. 481-489, March 2002
20. A. Lochtefeld, D. A. Antoniadis, "On the Experimental Determination of Carrier Velocity in Deeply Scaled NMOS: How Close to the Thermal imit ? ", IEEE Electron Device Letters, vol. 22, pp. 95-97, February 2001
21. M. J. Chen, H. T. Huang, K. C. Huang, P. N. Chen, C. S. Chang, C. H. Diasz, "Temperature Dependent Channel Backscattering Coefficient in Nanoscale MOSFETs", Proc. IEDM 2002, pp. 39
22. V. Barrai, T. Poiroux, M. Vinet, J. Widiez, B. Previtaly, P. Grosgeorges, G. Le Carval, S. Barraud, S. Deleonibus, J. L. Autran, D. Munteanu, "Experimental Determination of the channel Backscattering Coefficient in 10 nm-Metal-Gate Double-Gate Transistors", Proc. ULIS 2006
23. M. De Michielis, D. Esseni, F. Driussi, "Trade-Off between Electron Velocity and Density of States in Ballistic nano-MOSFETs", Proc ESSDERC 2005, pp. 165
24. S. Luryi, "Quantum Capacitance Devices", Appl. Phys. Lett, vol. 52 (6), pp. 501-503, February 1988
25. J. H. Rhew, Z. Ren, M. S. Lundstrom, "A Numerical study of Ballistic Transport in a Nanoscale MOSFET", Solid-State electronics, vol. 46, pp. 1899-1906, 2002
26. S. Takagi, "Subband Structure Engineering for Realizing Scaled CMOS with High Performance and Low Power Consumption" IEICE TE, vol. E85-C, pp. 1064, 2002
27. y Substrates", Physical Review B, vol. 48(19), pp. 14276-14287, 1993
28. S. Mudanai, L. F. Register, A. F. Tasch, S. K. Banerjee, "Understanding the effects of Wave Function Penetration on the Inversion Layer Capacitance of NMOSFETs", IEEE Electron Device Letters, vol. 22,pp. 145-147, 2001
29. I. Polishchuk, C. Hu, "Electron Wave function Penetration into Gate Dielectric and Interface Scattering- An Alternative to Surface Roughness Scattering Model", Proc VLSI 2001
30. S. Monfray; Skotnicki-T; Fenouillet-Beranger-C; Carriere-N; Chanemougame-D; Morand-Y; Descombes-S; Talbot-A; Dutartre-D; Jenny-C; Mazoyer-P; Palla-R; Leverd-F; Le-Friec-Y; Pantel-R; Borel-S; Louis-D; Buffet-N, "Emerging silicon-on-nothing (SON) devices technology" Solid-State-Electronics, vol. 48 pp. 887-895, 2004.