Using process-level redundancy to exploit multiple cores for transient fault tolerance

Proceedings of the International Conference on Dependable Systems and Networks

Volumn , Issue , 2007, Pages 297-306

  Shye, Alex ^a   Moseley, Tipp ^a   Reddi, Vijay Janapa ^b   Blomstedt, Joseph ^a   Connors, Daniel A ^a  

^a UCB 450   (United States)

^b HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PROCESS-LEVEL REDUNDANCY (PLR); SOFTWARE EXECUTION; TRANSIENT FAULT TOLERANCE;

COMPUTER HARDWARE; COMPUTER SOFTWARE; FAULT DETECTION; MICROPROCESSOR CHIPS; SOFTWARE PROTOTYPING;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 36049011017     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSN.2007.98     Document Type: Conference Paper

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