Chip multiprocessor architecture: Techniques to improve throughput and latency

Synthesis Lectures on Computer Architecture

Volumn 3, Issue , 2007, Pages 1-149

  Olukotun, Kunle ^a   Hammond, Lance ^a   Laudon, James ^b  

^a STANFORD UNIVERSITY   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

Application classes: throughput sensitive applications; Basic terms: chip multiprocessors (CMPs); Latency sensitive applications; Microprocessor power; Multi core microprocessors; Parallel processing; Server applications; Threaded execution

Indexed keywords

COMPUTER SOFTWARE; ENERGY DISSIPATION; ERROR ANALYSIS; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; PROBLEM SOLVING; SERVERS;

CHIP MULTIPROCESSORS (CMP); LATENCY-SENSITIVE APPLICATIONS; MICROPROCESSOR POWER; MULTI-CORE MICROPROCESSORS; SERVER APPLICATIONS; THREADED EXECUTION; THROUGHPUT-SENSITIVE APPLICATIONS;

COMPUTER ARCHITECTURE;

EID: 35748948044     PISSN: 19353235     EISSN: 19353243     Source Type: Book Series    
DOI: 10.2200/s00093ed1v01y200707cac003     Document Type: Review

References (76)

1. G. E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, no. 8, pp. 114-117, Apr. 19, 1965.
2. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 3rd edition. San Francisco, CA: Morgan Kaufmann, 2003.
3. D. W. Wall, "Limits of instruction-level parallelism," WRL Research Report 93/6, Digital Western Research Laboratory, Palo Alto, CA, 1993.
4. K. Yeager et al., "R10 000 superscalar microprocessor," presented at Hot Chips VII, Stanford, CA, 1995.
5. B. A. Nayfeh, L. Hammond, and K. Olukotun, "Evaluating alternatives for a multiprocessor microprocessor," in Proceedings of 23rd Int. Symp. Computer Architecture, Philadelphia, PA, 1996, pp. 66-77.
6. S. Amarasinghe et al., "Hot compilers for future hot chips," in Hot Chips VII, Stanford, CA, Aug. 1995. http://www.hotchips.org/ archives/
7. J. Ousterhout, "Why aren't operating systems getting faster as fast as hardware?" in Summer 1990 USENIX Conference, June 1990, pp. 247-256.
8. Standard Performance Evaluation Corporation, SPEC, http://www.spec.org, Warrenton, VA.
9. L. Barroso, J. Dean, and U. Hoezle, "Web search for a planet: the architecture of the Google cluster," IEEE Micro., Vol. 23, No. 2, pp. 22-28, Mar-Apr. 2003. doi:/10.1109/MM.2003.1196112
10. K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang, "The case for a single chip multiprocessor," in Proc. 7th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII), Cambridge, MA, Oct. 1996, pp. 2-11.
11. S. Kapil, "UltraSPARC Gemini: dual CPU processor," in Hot Chips 15, Stanford, CA, Aug. 2003. http://www.hotchips.org/archives/
12. T. Maruyama, "SPARC64 VI: Fujitsu's Next Generation Processor," in Microprocessor Forum, San Jose, CA, Oct. 2003.
13. C. McNairy and R. Bhatia, "Montecito: the next product in the Itanium Processor Family," in Hot Chips 16, Stanford, CA, Aug. 2004. http://www.hotchips.org/archives/
14. C. Moore, "POWER4 system microarchitecture," in Microprocessor Forum, San Jose, CA, Oct. 2000.
15. L. A. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese, "Piranha: a scalable architecture based on single-chip multiprocessing," in Proc. 27th Int. Symp. Computer Architecture (ISCA-27), Vancouver, BC, Canada, June 2000, pp. 282-293.
16. J. Lo, L. Barroso, S. Eggers, K. Gharachorloo, et al. "An analysis of database workload performance on simultaneous multithreaded processors," in Proc. 25th Annu. Int. Symp. Computer Architecture (ISCA-25), Barcelona, Spain, June 1998, pp. 39-50.
17. S. Kunkel, R. Eickemeyer, M. Lip, and T. Mullins, "A performance methodology for commercial servers," IBM J. Res. Dev., Vol. 44, No. 6, Nov. 2000, pp. 851-872.
18. T. Agerwala and S. Chatterjee, "Computer architecture: challenges and opportunities for the next decade," IEEE Micro, Vol. 25, No. 3, pp. 58-69, May/June 2005. doi:10.1109/MM.2005.45
19. P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: a 32-way multithreaded SPARC processor," IEEE Micro, Vol. 25, No. 2, Mar./Apr. 2005, pp. 21-29. doi:10.1109/MM.2005.35
20. J. Clabes, J. Friedrich, and M. Sweet, "Design and implementation of the POWER5™ Microprocessor," in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2004, pp. 56-57.
21. J. D. Davis, et al. "Maximizing CMT throughput with Mediocre cores," in Proc. 14th Int. Conf Parallel Architectures and Compilation Techniques, St. Louis, MO, Sept. 2005, pp. 51-62.
22. D. Marr, "Hyper-threading technology in the Netburst Microarchitecture," in Hot Chips XIV, Stanford, CA, Aug. 2002. http://www.hotchips.org/archives/
23. A. Agarwal, J. Kubiatowicz, D. Kranz, B.-H. Lim, D. Yeung, G. D'Souza, and M. Parkin, "Sparcle: an evolutionary processor design for large-scale multiprocessors," IEEE Micro, Vol. 13, No. 3, June 1993, pp. 48-61. doi:10.1109/40.216748
24. J. Laudon, A. Gupta, and M. Horowitz, "Interleaving: a multithreading technique targeting multiprocessors and workstations," in Proc. 6th Int. Symp. Architectural Support for Parallel Languages and Operating Systems (ASPLOS-VI), San Jose, CA, Oct. 1994, pp.308-318.
25. D. Tullsen, S. Eggers, and H. Levy, "Simultaneous multithreading: maximizing onchip parallelism," in Proc. 22nd Annu. Int. Symp. Computer Architecture (ISCA-22), Santa Margherita Ligure, Italy, June 1995, pp. 392-403.
26. S. Naffziger, T. Grutkowski, and B. Stackhouse, "The implementation of a 2-core multi-threaded Itanium® Family Processor," in Proc. of IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2005, pp. 182-183.
27. R. L. Sites and R. T. Witek, Alpha AXP Architecture Reference Manual, 2nd edition. Burlington, MA: Digital Press, 1995.
28. N. P. Jouppi and S. Wilton, "Tradeoffs in two-level on-chip caching," in 21st Annu. Int. Symp. Computer Architecture (ISCA-21), Chicago, IL, Apr. 1994, pp. 34-45.
29. Transaction Processing Performance Council. TPC Benchmark B, Standard Specification Revision 2.0, June 1994.
30. Transaction Processing Performance Council. TPC Benchmark D (Decision Support) Standard Specification Revision 1.2, Nov. 1996.
31. L. A. Barroso, K. Gharachorloo, and E. Bugnion. "Memory system characterization of commercial workloads," in 25th Annu. Int. Symp. Computer Architecture, Barcelona, Spain, June 1998, pp. 3-14.
32. M. Rosenblum, E. Bugnion, S. Herrod, and S. Devine, "Using the SimOS machine simulator to study complex computer systems," ACM Trans. Model. Comput. Simul., Vol. 7, No. 1, pp. 78-103, Jan. 1997. doi: 10.1145/244804.244807
33. Transaction Processing Performance Council. TPC Benchmark C, Standard Specification Revision 3.6, Oct. 1999.
34. J. Laudon, "Performance/Watt: the new server focus," in Proc. Workshop on Design, Architecture, and Simulation of Chip Multiprocessors, Barcelona, Spain, Nov. 2005.
35. Standard Performance Evaluation Corporation, SPEC, http://www.spec.org, Warrenton, VA.
36. Transaction Processing Performance Council, TPC, http://www.tpc.org, San Francisco, CA.
37. "XML Processing Performance in Java and .Net," http://java.sun.com/performance/ reference/whitepapers/XML.Test-1_0.pdf
38. T. Sherwood, S. Sair, and B. Calder, "Phase tracking and prediction," in 30th Annu. Int. Symp. Computer Architecture, San Diego, CA, June 2003, pp. 336-347.
39. A. R. Alameldeen and D. A. Wood, "Variability in architectural simulations of multi-threaded workloads," in 9th Int. Symp. High Performance Computer Architecture (HPCA), Anaheim, CA, Feb. 2003.
40. R. S. Chappell, F. Tseng, A. Yoaz, and Y. N. Patt, "Difficult-path branch prediction using subordinate microthreads," in Proc. 29th Annual Int. Symp. Computer Architecture, Anchorage, AK, June 2002, pp. 307-317.
41. D. Kim, S. S. Liao, P. H. Wang, J. del Cuvillo, X. Tian, X. Zou, H. Wang, D. Yeung, M. Girkar, and J. P. Shen, "Physical experimentation with prefetching helper threads on Intel's hyper-threaded processors," in Proc. Int. Symp. Code Generation and Optimization (CGO 2004), Palo Alto, CA, Mar. 2004, pp. 27-38.
42. Y. Song, S. Kalogeropulos, and P. Tirumalai, "Design and implementation of a compiler framework for helper threading on multi-core processors," in Proc. 14th Int. Conf on Parallel Architectures and Compilation Techniques (PACT-2005), St. Louis, MO, Sept. 2005, pp. 99-109.
43. C.-K. Luk, "Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors," in Proc. 28th Annual Int. Symp. Computer Architecture (ISCA-28), Göteborg, Sweden, June 2001, pp. 40-51.
44. Standard Performance Evaluation Corporation, SPEC, http://www.spec.org, Warrenton, VA.
45. G. Sohi, S. Breach, and T. Vijaykumar, "Multiscalar processors," in Proc. 22nd Annual Int. Symp. Computer Architecture, Santa Margherita Ligure, Italy, June 1995, pp. 414-425.
46. B. Nayfeh, L. Hammond, and K. Olukotun, "Evaluation of Design Alternatives for a Multiprocessor Microprocessor," in Proc. of23rd Annual Int. Symp. Computer Architecture, Philadelphia, PA, June 1996, pp. 66-77.
47. M. Franklin and G. Sohi, "ARB: a hardware mechanism for dynamic reordering of memory references," IEEE Trans. Comput., Vol. 45, No. 5, May 1996, pp. 552-571. doi: 10.1109/12.509907
48. S. Gopal, T. N. Vijaykumar, J. E. Smith, and G. S. Sohi, "Speculative versioning cache," in Proc. 4th Int. Symp. High-Performance Computer Architecture (HPCA-4), Las Vegas, NV, February 1998.
49. N. P. Jouppi, "Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers," in Proc. 17th Annu. Int. Symp. Computer Architecture, Seattle, WA, June 1990, pp. 364-373.
50. S. Muchnick, Advanced Compiler Design and Implementation. San Mateo, CA: Morgan Kaufmann, 1997.
51. K. Olukotun, L. Hammond, and M. Willey, "Improving the performance of speculatively parallel applications on the hydra CMP," in Proc. 1999 Int. Conf Supercomputing, Rhodes, Greece, June 1999, pp. 21-30.
52. K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang, "The case for a single chip multiprocessor," in Proc. 7th Int. Conf Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII), Cambridge, MA, Oct. 1996, pp. 2-11.
53. M. Tremblay, "MAJC™: an architecture for the new millennium," in Hot Chips XI, Stanford, CA, Aug. 1999, pp. 275-288. http://www.hotchips.org/archives/. Also reported in B. Case, "Sun makes MAJC with mirrors," Microprocessor Report, Oct. 25, 1999, pp. 18-21.
54. L. Hammond, M. Willey, and K. Olukotun, "Data speculation support for a chip multiprocessor," in Proc. 8th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), San Jose, CA, Oct. 1998, pp. 58-69.
55. J. G. Steffan et al., "A scalable approach to thread-level speculation," in Proc. 27th Ann. Int. Symp. Computer Architecture (ISCA-27), Vancouver, BC, Canada, June 2000, pp. 1-12.
56. T. Wilkinson, Kaffe Virtual Machine, http://kaffe.org, 1997-2002.
57. http://www.byte.com
58. http://www.specbench.org/jvm98/
59. http://www.epcc.ed.ac.uk/javagrande/
60. L. Hammond, B. D. Carlstrom, V. Wong, M. Chen, C. Kozyrakis, and K. Olukotun, "Transactional coherence and consistency: simplifying parallel hardware and software," IEEE Micro, Vol. 24, No. 6, Nov.-Dec. 2004, pp. 92-103. doi:10.1109/MM.2004.91
61. L. Hammond, B. Hubbert, M. Siu, M. Prabhu, M. Chen, and K. Olukotun, "The Stanford Hydra CMP," IEEE Micro., Vol. 20, No. 2, Mar-Apr. 2000, pp. 71-84. doi: 10.1109/40.848474
62. V. Krishnan and J. Torrellas, "A chip multiprocessor architecture with speculative multithreading," IEEE Trans. Comput., Vol. 48, No. 9, Sept. 1999, pp. 866-880. doi:10.1109/12.795218
63. G. Sohi, S. Breach, and T. Vijaykumar, "Multiscalar processors," in Proc. 22nd Annual Int. Symp. Computer Architecture, Santa Margherita Ligure, Italy, June 1995, pp. 414-425.
64. J. G. Steffan and T. Mowry, "The potential for using thread-level data speculation to facilitate automatic parallelization," in Proc. 4th Int. Symp. High-Performance Computer Architecture (HPCA-4), Las Vegas, NV, Feb. 1998, pp. 2-13.
65. J. F. Martinez and J. Torrellas, "Speculative synchronization: applying thread-level speculation to explicitly parallel applications," in Proc. 10th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), San Jose, CA, Oct. 2002, pp. 18-29.
66. A. Zhai, C. B. Colohan, J. G. Steffan, and T. C. Mowry, "Compiler optimization of scalar value communication between speculative threads," in Proc. 10th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), San Jose, CA, Oct. 2002, pp. 171-183.
67. T. Sherwood and B. Calder, "Time varying behavior of programs," Dept. of Computer Science and Eng., UCSD, Tech. Rep. No. CS99-630, Aug. 1999.
68. M. K. Prabhu and K. Olukotun, "Exposing speculative thread parallelism in SPEC2000," in Proc. Principles and Practices of Parallel Programming 2005 (PPoPP 05), Chicago, IL, June 2005.
69. T. Wilkinson, Kaffe Virtual Machine, http://kaffe.org, 1997-2002.
70. M. K. Chen and K. Olukotun, "The Jrpm system for dynamically parallelizing Java programs," in Proc. 30th Int. Symp. Computer Architecture (ISCA-30), San Diego, CA, June 2003, pp. 434-445.
71. S. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH2 programs: characterization and methodological considerations," in Proc. 22nd Int. Symp. Computer Architecture (ISCA-22), Santa Margherita Ligure, Italy, June 1995, pp. 24-36.
72. D. O'Hallaron, "Spark98: sparse matrix kernels for shared memory and message passing systems," School of Computer Science, Carnegie Mellon University, Tech. Rep. CMUCS-97-178, Oct. 1997.
73. J. R. Larus and R. Rajwar, Transactional Memory. San Rafael, CA: Morgan & Claypool Publishers, 2006.
74. R. Rajwar and J. Goodman, "Transactional lock-free execution of lock-based programs," in Proc. 10th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS), San Jose, CA, Oct. 2002, pp. 5-17.
75. R. Kumar, D. Tullsen, N. Jouppi, and P. Ranganathan, "Heterogeneous chip multiprocessors," IEEE Computer, Vol. 38, No. 11, Nov. 2005, pp. 32-38.
76. J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy, "Introduction to the CELL multiprocessor," IBM J. Res. Dev., Vol. 49, No. 4/5, pp. 589-604, Sept. 2005.