Transactional coherence and consistency: Simplifying parallel hardware and software

IEEE Micro

Volumn 24, Issue 6, 2004, Pages 92-103

  Hammond, Lance ^a   Carlstrom, Brian D ^a   Wong, Vicky ^a   Chen, Michael ^a   Kozyrakis, Christos ^a   Olukotun, Kunle ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SOFTWARE; MATHEMATICAL MODELS; VLSI CIRCUITS;

PARALLEL ARCHITECTURE DESIGN; PARALLEL PROGRAMMING;

PARALLEL PROCESSING SYSTEMS;

EID: 15044358803     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2004.91     Document Type: Article

References (6)

1. R. Rajwar and J. Goodman, "Transactional Lock-Free Execution of Lock-Based Programs," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 02), ACM Press 2002, pp. 5-17.
2. M. Herlihy and J. Moss, "Transactional Memory: Architectural Support for Lock-Free Data Structures," Proc. 20th Int'l Symp. Computer Architecture (ISCA 93), ACM Press, 1993, pp. 289-300.
3. J. Martinez and J. Torrellas, "Speculative Synchronization: Applying Thread-Level Speculation to Parallel Applications," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 02), ACM Press, 2002, pp. 18-29
4. M.K. Chen and K. Olukotun, "The Jrpm System for Dynamically Parallelizing Java Programs," Proc. 30th Int'l Symp. Computer Architecture (ISCA 03), IEEE CS Press, 2003, pp. 434-445.
5. L. Hammond et al., "Programming with Transactional Coherence and Consistency (TCC)," Proc. 11th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 04), ACM Press, 2004, pp. 1-13.
6. L. Hammond et al., "Transactional Memory Coherence and Consistency," Proc. 31st Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, pp. 102-113.