Ultra-shallow junctions for novel device architectures beyond 65nm node

Extended Abstracts of the Fourth International Workshop on Junction Technology, IWJT 2004

Volumn 4, Issue , 2004, Pages 335-340

  Agarwal, Aditya ^a   Gossmann, Hans ^a  

^a AXCELIS TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEPOSITION; DIFFUSION IN SOLIDS; ELECTRIC FIELD EFFECTS; EPITAXIAL GROWTH; HEAT CONDUCTION; ION IMPLANTATION; MOSFET DEVICES; PATTERN RECOGNITION; RAPID THERMAL ANNEALING; SILICON WAFERS; THICKNESS MEASUREMENT; THRESHOLD VOLTAGE;

METAL GATES; PATTERN DENSITY; TEMPERATURE DIFFERENCE; WAFER TEMPERATURE;

GATES (TRANSISTOR);

EID: 3543058871     PISSN: None     EISSN: None     Source Type: Book    
DOI: None     Document Type: Conference Paper

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