Compact FD-SOI MOSFETs fabrication process featuring SixGe1-x gate and damascene-dummy SAC

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2000, Pages 208-209

  Hisamoto, Digh ^a   Kachi, Tsuyosi ^a   Tsujikawa, Shinpei ^a   Miyauchi, Akihiro ^a   Kusukawa, Kikuo ^a   Sakuma, Noriyuki ^a   Homma, Yoshio ^a   Yokoyama, Natsuki ^a   Ootsuka, Fumio ^a   Onai, Takahiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); MOSFET DEVICES; SEMICONDUCTING SILICON COMPOUNDS; THRESHOLD VOLTAGE;

SELF-ALIGN CONTACT (SAC);

SILICON ON INSULATOR TECHNOLOGY;

EID: 0033683681     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)