Advanced gate-stack architecture for low-voltage dual-workfunction CMOS technologies with shallow trench isolation

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1997, Pages 71-72

  Schwalke, U ^a   Kerber, M ^a   Koller, K ^a   Ludwig, B ^a   Seidl, A ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; DIFFUSION IN SOLIDS; ELECTRONICS PACKAGING; GATES (TRANSISTOR); OXIDES; SEMICONDUCTOR DOPING; THERMAL CYCLING;

EXTENDED TRENCH ISOLATION GATE TECHNOLOGY (EXTIGATE); SHALLOW TRENCH ISOLATION (STI);

CMOS INTEGRATED CIRCUITS;

EID: 0030708104     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.1997.623700     Document Type: Conference Paper

References (4)