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Volumn 1, Issue , 2004, Pages

Testing high resolution ADCs using deterministic dynamic element matching

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; COMPUTER SIMULATION; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; MIXER CIRCUITS; SEMICONDUCTING SILICON; SIGNAL ENCODING; SIGNAL GENERATORS; THERMOMETERS; VECTORS;

EID: 4344580623     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (4)

References (13)
  • 3
    • 0036287087 scopus 로고    scopus 로고
    • A modified histogram approach for accurate self-characterization of analog-to-digital converters
    • Arizona, May
    • K. L. Parthasarathy, Le Jin, D. Chen and R. L. Geiger, "A Modified Histogram Approach for Accurate Self-Characterization of Analog-to-Digital Converters", Proceedings of 2002 IEEE ISCAS, Arizona, May 2002.
    • (2002) Proceedings of 2002 IEEE ISCAS
    • Parthasarathy, K.L.1    Jin, L.2    Chen, D.3    Geiger, R.L.4
  • 5
    • 0034466238 scopus 로고    scopus 로고
    • Very linear ramp-generators for high resolution ADC BIST and calibration
    • Jing Wang, E. Sanchez-Sinencio, F. Maloberti, "Very linear ramp-generators for high resolution ADC BIST and calibration" Proceedings IEEE MWSCAS, Volume: 2, 2000.
    • (2000) Proceedings IEEE MWSCAS , vol.2
    • Wang, J.1    Sanchez-Sinencio, E.2    Maloberti, F.3
  • 6
    • 0020272819 scopus 로고
    • A Monolithic 14 Bit A/D Converter
    • December
    • R. J. Van De Plassche and H. J Schouwenaars, "A Monolithic 14 Bit A/D Converter". IEEE JSSC, Vol. SC-17, No. 6, December 1982.
    • (1982) IEEE JSSC , vol.SC-17 , Issue.6
    • Van De Plassche, R.J.1    Schouwenaars, H.J.2
  • 7
    • 0024645333 scopus 로고
    • A noise-shaping coder topology for 15+ bit converters
    • April
    • L. R. Carley, "A Noise-Shaping Coder Topology for 15+ Bit Converters" IEEE JSSC, Vol. 24, No. 2, April 1989.
    • (1989) IEEE JSSC , vol.24 , Issue.2
    • Carley, L.R.1
  • 8
    • 0031647656 scopus 로고    scopus 로고
    • A low-complexity dynamic element matching DAC for direct digital synthesis
    • January
    • H. T. Jensen and I. Galton, "A Low-Complexity Dynamic Element Matching DAC for Direct Digital Synthesis." IEEE Transactions on Circuits and Systems, Vol. 45, January 1998.
    • (1998) IEEE Transactions on Circuits and Systems , vol.45
    • Jensen, H.T.1    Galton, I.2
  • 9
    • 0032308948 scopus 로고    scopus 로고
    • A 113-db SNR oversampling DAC with segmented noise-shaped scrambling
    • December
    • R. Adams, K. Q. Nguyen and K. Sweetland, "A 113-db SNR Oversampling DAC with Segmented Noise-Shaped Scrambling." IEEE JSSC, Vol. 33, No. 12, December 1998.
    • (1998) IEEE JSSC , vol.33 , Issue.12
    • Adams, R.1    Nguyen, K.Q.2    Sweetland, K.3
  • 10
    • 0034251567 scopus 로고    scopus 로고
    • A 14-bit current-mode ΣΔ DAC based upon rotated data weighted averaging
    • August
    • R. E. Radke, A. Eshragni and T. S. Fiez, "A 14-Bit Current-Mode ΣΔ DAC Based Upon Rotated Data Weighted Averaging." IEEE JSSC. Vol. 35, August 2000.
    • (2000) IEEE JSSC , vol.35
    • Radke, R.E.1    Eshragni, A.2    Fiez, T.S.3
  • 11
    • 4344661707 scopus 로고    scopus 로고
    • A dynamic element matching approach to ADC testing
    • Tulsa
    • B. Olleta, D. Chen, and R. L. Geiger, "A Dynamic Element Matching Approach to ADC Testing". IEEE MWSCAS, Tulsa, 2002.
    • (2002) IEEE MWSCAS
    • Olleta, B.1    Chen, D.2    Geiger, R.L.3
  • 13
    • 0036292808 scopus 로고    scopus 로고
    • Formulation of INL and DNL yield estimation in current-steering D/A converters
    • 26-29 May
    • Y. Cong and R. L. Geiger, "Formulation of INL and DNL yield estimation in current-steering D/A converters", 2002 IEEE ISCAS, Volume: 3, 26-29 May 2002.
    • (2002) 2002 IEEE ISCAS , vol.3
    • Cong, Y.1    Geiger, R.L.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.