A power-efficient clock and data recovery circuit in 0.18 μm CMOS technology for multi-channel short-haul optical data communication

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 10, 2007, Pages 2235-2244

  Tajalli, Armin ^a,b,c   Muller, Paul ^a,c,d   Leblebici, Yusuf ^a,c  

^a IEEE

^b SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

^c EPFL   (Switzerland)

^d Marvell Semiconductor   (Switzerland)

Author keywords

Chip to chip interconnection; Clock and data recovery circuit; CMOS integrated circuits; Frequency tolerance; Gated oscillator; Jitter tolerance; Optical data communication; Short haul

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; ERROR DETECTION; JITTER; PHASE LOCKED LOOPS; TUNING;

CLOCK AND DATA RECOVERY CIRCUIT; FREQUENCY TOLERANCE (FTOL); GATED-OSCILLATOR-BASED CLOCK AND DATA RECOVERY CIRCUITS (GO CDRS); JITTER TOLERANCE (JTOL); PSEUDO-RANDOM BIT STREAM (PRBS) INPUT DATA;

OPTICAL DATA PROCESSING;

EID: 34748826708     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.905234     Document Type: Conference Paper

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