A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 2, 2005, Pages 462-470

  Kim, Jinwook ^a,b   Yang, Jeongsik ^a   Byun, Sangjin ^a,c   Jun, Hyunduk ^a,b   Park, Jeongkyu ^a,b   Conroy, Cormac S G ^a   Kim, Beomsup ^a  

^a Berkana Wireless   (United States)

^b Berkäna Korea   (South Korea)

^c Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

Adaptive equalizer; Clock data recovery (CDR); Serial link transceiver

Indexed keywords

ADAPTIVE ALGORITHMS; ADAPTIVE SYSTEMS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; EQUALIZERS; LARGE SCALE SYSTEMS; PHASE LOCKED LOOPS; SIGNAL DISTORTION; SIGNAL PROCESSING;

ADAPTIVE EQUALIZERS; CLOCK DATA RECOVERY (CDR); PHASE INTERPOLATOR; PHASE QUANTIZATION ERRORS; SERIAL-LINK TRANSCEIVER;

TRANSCEIVERS;

EID: 13444251352     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.841037     Document Type: Article

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