A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 5, 2004, Pages 795-803

  Moon, Yongsam ^a   Park, Young Soo ^a   Kim, Namhoon ^a   Ahn, Gijung ^a   Shin, Hyun J ^a   Jeong, Deog Kyoon ^b  

^a Silicon Image Inc   (United States)

^b Seoul National University   (South Korea)

Author keywords

Backplane transceiver; Clock and data recovery (CDR); Coarse tuning; Delay locked loop (DLL); Folded starved inverter; Phase locked loop (PLL); Pre emphasis; Serial link

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); JITTER; PHASE LOCKED LOOPS; SIGNAL INTERFERENCE; VARIABLE FREQUENCY OSCILLATORS;

BACKPLANE TRANSCEIVERS; CLOCK AND DATA RECOVERY; DELAY LOCKED LOOP (DLL); FOLDED STARVED INVERTERS; SERIAL LINK;

TRANSCEIVERS;

EID: 2442425566     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.826311     Document Type: Article

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