A multibitrate burst-mode CDR circuit with bit-rate discrimination function from 52 to 1244 Mb/s

IEEE Photonics Technology Letters

Volumn 13, Issue 11, 2001, Pages 1221-1223

  Kobayashi, Shoukei ^a,b   Hashimoto, Masashi ^b  

^a IEEE   (Japan)

^b NTT CORPORATION   (Japan)

Author keywords

Bit rate discrimination circuit; Clock and data recovery circuit; Multibit rate

Indexed keywords

CLOCK AND DATA RECOVERY (CDR) CIRCUITS;

BIT ERROR RATE; MULTIPLEXING; OSCILLATORS (ELECTRONIC);

PACKET NETWORKS;

EID: 0035503589     PISSN: 10411135     EISSN: None     Source Type: Journal    
DOI: 10.1109/68.959370     Document Type: Article

References (9)

1. Multi-bit-rate passive double star system using time-unit packet
2. A burst-mode packet receiver with bit-rate-discriminating circuit for multi-bit-rate transmission system
3. Multibitrate access technique for upgradable PDS system
4. A 0.155, 0.622 and 2.488 Gb/s automatic bit rate selecting clock and data recovery IC for bit rate transparent SDH-systems
5. An auto-ranging 50-210 Mb/s clock recovery circuit with a time-to-digital converter
6. A 156 Mb/s cmos clock recovery circuit for burst-mode transmission
7. Clock recovery circuits with instantaneous locking
8. Bit-rate detection circuit for rapidly reconfigurable rate-transparent optical networks
9. 150/30 Mb/s CMOS nonoversampled clock and data recovery circuits with instantaneous locking and jitter rejection