A 10Gb/s burst-mode CDR IC in 0.13μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Nogawa, Masafumi ^a   Nishimura, Kazuyoshi ^a   Kimura, Shunji ^a   Yoshida, Tomoaki ^a   Kawamura, Tomoaki ^a   Togashi, Minoru ^a   Kumozaki, Kiyomi ^a   Ohtomo, Yusuke ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144450202     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. S. Kimura, et al., "10-Gb/s Burst-Mode Clock and Data Recovery Units for Optical Packet-Based Systems," ECOC 2002, vol. 3, 8.2.5, Sept., 2002.
2. Q. Le, et al., "Burst-Mode Receiver for 1.25Gb/s Ethernet PON with AGC and Internally Created Reset Signal," ISSCC Dig. Tech. Papers, pp. 474-475, Feb., 2004.
3. M. Nakamura, N. Ishihara and Y. Akazawa, "A 156 Mbps CMOS Clock Recovery Circuit for Burst-mode Transmission," Symp. VLSI Circuits, pp. 122-123, Jun., 1996.
4. S. Kimura, et al., "10-Gb/s Burst-Mode Clock and Data Recovery IC for a WDM/TDM-PON Access Network," accepted for publication in LEOS 2004, Nov., 2004.
5. Y. Ohtomo, et al., "A 12.5Gb/s CMOS BER Test Using a Jitter-Tolerant Parallel CDR," ISSCC Dig. Tech. Papers, pp. 174-175, Feb., 2004.