A CMOS Multichannel 10-Gb/s Transceiver

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 12, 2003, Pages 2094-2100

  Takauchi, Hideki ^a   Tamura, Hirotaka ^a   Matsubara, Satoshi ^a   Kibune, Masaya ^a   Doi, Yoshiyasu ^a   Chiba, Takaya ^a   Anbutsu, Hideaki ^a   Yamaguchi, Hisakatsu ^a   Mori, Toshihiko ^a   Takatsu, Motomu ^a   Gotoh, Kohtaroh ^a   Sakai, Toshiaki ^a   Yamamura, Takeshi ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

CMOS integrated circuits; Current mode logic; High speed integrated circuits; Phase control; Phase locked loops (PLLs)

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; ERROR ANALYSIS; INTEGRATED CIRCUITS; LOGIC CIRCUITS; MULTIPLEXING; PHASE CONTROL; PHASE LOCKED LOOPS; TELECOMMUNICATION; TRANSMITTERS;

CURRENT-MODE LOGICS; HIGH-SPEED INTEGRATED CIRCUITS; PSEUDORANDOM BIT SEQUENCE (PRBS);

TRANSCEIVERS;

EID: 9144230706     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.818577     Document Type: Conference Paper

References (4)

1. M. M. Green et al., "OC-192 transmitter in standard 0.18 μm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol. 45, Feb. 2002, pp. 248-249.
2. S. Sidiropoulos et al., "A semidigital dual delay-locked loop, " IEEE J. Solid-State Circuits, vol. 32, pp. 1083-1092, Nov. 1997.
3. H. Tamura et al., "5-Gb/s bidirectional balanced-line link compliant with plesiochronous clocking," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2001, pp. 50-51.
4. SONET OC-192, Transport System Generic Criteria, OR-1377-CORE no. 4, Bellcore, Piscataway, NJ, Mar. 1998.