A 50-mW/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface With Digital Eye-Tracking

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 4, 2004, Pages 613-621

  Miki, Yoshio ^a   Saito, Tatsuya ^a   Yamashita, Hiroki ^a   Yuki, Fumio ^a   Baba, Takashige ^a   Koyama, Akio ^a   Sonehara, Masahito ^a  

^a HITACHI LTD   (Japan)

Author keywords

0.18 m SiGe BiCMOS technology; Data recovery; Digital phase locked loop (PLL); Eye tracking; High frequency jitter; Interface; Jitter tolerance; Long term wander; SFI 5

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); DIGITAL CIRCUITS; ELECTRIC POWER UTILIZATION; JITTER; PHASE LOCKED LOOPS; PRINTED CIRCUIT DESIGN;

0.18-ΜM SIGE BICMOS TECHNOLOGY; DATA RECOVERY; DIGITAL PHASE-LOCKED LOOP (PLL); EYE-TRACKING; HIGH-FREQUENCY JITTERS; JITTER TOLERANCES; LONG-TERM WABDER; SFI-5;

OPTICAL COMMUNICATION;

EID: 16544391001     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.824704     Document Type: Article

References (8)

1. Optical Internetworking Forum Document, Implementation Agreement OIF-SFI5-01.0, Jan. 2002.
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5. T. Saito et al., "A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface using novel eye-tracking method," in Symp. VLSI Circuits Dig. Tech. Papers, June 2003, pp. 57-60.
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