A Second-Order Semidigital Clock Recovery Circuit Based on Injection Locking

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 12, 2003, Pages 2101-2110

  Ng, Hiok Tiaq ^a   Farjad Rad, Ramin ^a   Lee, M J Edward ^a   Dally, William J ^a,b   Greer, Trey ^a   Poulton, John ^a   Edmondson, John H ^a   Rathi, Rohit ^a   Senthinathan, Ramesh ^a,c  

^a Velio Communications Inc   (United States)

^b STANFORD UNIVERSITY   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

Clock and data recovery (CDR); Clock multiplication; Frequency tracking acquisition; High speed transceivers; Injection locking; Jitter filtering; Multiplying delay locked loop (MDLL); Phase interpolation

Indexed keywords

ACOUSTIC NOISE; ATTENUATION; BANDWIDTH; CAPACITORS; CATHODE RAY OSCILLOSCOPES; HEAT LOSSES; INTERPOLATION; MULTIPLEXING; MULTIPLYING CIRCUITS; OSCILLATORS (ELECTRONIC); SIGNAL FILTERING AND PREDICTION; TIMING JITTER; TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK MULTIPLICATION; HIGH-SPEED TRANSCEIVERS; INJECTION LOCKING; JITTER FILTERING; MULTIPLYING DELAY-LOCKED LOOPS (MDLL); PHASE INTERPOLATION;

CMOS INTEGRATED CIRCUITS;

EID: 0346972304     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.818576     Document Type: Conference Paper

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