메뉴 건너뛰기




Volumn , Issue , 2005, Pages 193-196

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0. 18μm digital CMOS technology

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA ACQUISITION; DIGITAL DEVICES; ELECTRIC CLOCKS; PRODUCT DESIGN; SIGNAL RECEIVERS;

EID: 33749188080     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2005.1541592     Document Type: Conference Paper
Times cited : (6)

References (11)
  • 1
    • 9144230706 scopus 로고    scopus 로고
    • A CMOS multichannel 10-Gb/s transceiver
    • December
    • H. Takauchi, and et al., "A CMOS multichannel 10-Gb/s transceiver," IEEE J. of Solid-State Circuits, vol. 38, pp. 2094-2100, December 2003.
    • (2003) IEEE J. of Solid-state Circuits , vol.38 , pp. 2094-2100
    • Takauchi, H.1
  • 2
    • 0029723441 scopus 로고    scopus 로고
    • A 156 Mbps CMOS clock recovery circuit for burst-mode transmission
    • M. Nakamura, and et al., "A 156 Mbps CMOS clock recovery circuit for burst-mode transmission," IEEE Symp. On VLSI Circuits Digest of Technical Papers, pp. 122-123, 1996.
    • (1996) IEEE Symp. on VLSI Circuits Digest of Technical Papers , pp. 122-123
    • Nakamura, M.1
  • 4
    • 0347382651 scopus 로고    scopus 로고
    • Multi-gigabit-rate clock and data recovery based in blind oversampling
    • December
    • J. Kim, and D. -K. Jeong, "Multi-gigabit-rate clock and data recovery based in blind oversampling," IEEE Comm. Mag., pp. 68-74, December 2003.
    • (2003) IEEE Comm. Mag. , pp. 68-74
    • Kim, J.1    Jeong, D.K.2
  • 7
    • 0032651134 scopus 로고    scopus 로고
    • Jitter and phase noise in ring oscillators
    • June
    • A. Hajimiri, and et al., "Jitter and phase noise in ring oscillators," IEEE J. of Solid-State Circuits, vol. 34, pp. 790-804, June 1999.
    • (1999) IEEE J. of Solid-state Circuits , vol.34 , pp. 790-804
    • Hajimiri, A.1
  • 8
    • 0242443400 scopus 로고    scopus 로고
    • A 5Gbps CMOS frequency tolerant multi phase clock recovery circuit
    • T. Iwata, and et al., "A 5Gbps CMOS frequency tolerant multi phase clock recovery circuit," IEEE Symp. on VLSI Circuits Digest of Technical Papers, pp. 82-83, 2002.
    • (2002) IEEE Symp. on VLSI Circuits Digest of Technical Papers , pp. 82-83
    • Iwata, T.1
  • 9
    • 16244388280 scopus 로고    scopus 로고
    • A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator
    • March
    • R. Kreienkamp, and et al., "A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator,"IEEE J. of Solid-State Circuits, vol. 40, pp. 736-743, March 2005.
    • (2005) IEEE J. of Solid-state Circuits , vol.40 , pp. 736-743
    • Kreienkamp, R.1
  • 10
    • 0035333506 scopus 로고    scopus 로고
    • A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector
    • May
    • J. Savoj, and B. Razavi, "A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector," IEEE J. of Solid-State Circuits, vol. 36, pp. 761-767, May 2001.
    • (2001) IEEE J. of Solid-state Circuits , vol.36 , pp. 761-767
    • Savoj, J.1    Razavi, B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.