Multi-Gigabit-Rate Clock and Data Recovery Based on Blind Oversampling

IEEE Communications Magazine

Volumn 41, Issue 12, 2003, Pages 68-74

  Kim, Jaeha ^a,b,c   Jeong, Deog Kyoon ^a,d  

^a Seoul National University   (South Korea)

^b True Circuits Inc   (United States)

^c Seoul National University   (South Korea)

^d TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK AND DATA RECOVERY UNIT (CDR); JITTER TOLERANCES;

ALGORITHMS; BIT ERROR RATE; COMPUTER SIMULATION; JITTER; LIMITERS; LOCAL AREA NETWORKS; STATISTICAL METHODS;

DATA TRANSFER;

EID: 0347382651     PISSN: 01636804     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCOM.2003.1252801     Document Type: Article

References (4)

1. IEEE, IEEE Std 802.3ae-2002, "IEEE Standard for Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications - Media Access Control (MAC) Parameters, Physical Layer and Management Parameters for 10 Gb/s Operation," Aug. 2002.
2. C.-K. K. Yang, R. Farjad-Rad, and M. A. Horowitz, "A 0.5-mm CMOS 4.0-Gb/s Serial Link Transceiver with Data Recovery using Oversampling," IEEE J. Solid-State Circuits, vol. 33, May 1998, pp. 713-22.
3. K. Lee et al., "A CMOS Serial Link for Fully Duplexed Data Communication," IEEE J. Solid-State Circuits, vol. 30, Apr. 1995, pp. 353-64.
4. S. Kim et al., "An 800Mb/s Multi-channel CMOS Serial Link with 3× Oversampling," Proc. IEEE 7995 Custom IC Conf., May 1995, pp. 451-54.