Low-power high-level synthesis for FPGA architectures

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 134-139

  Chen, Deming ^a   Cong, J ^a   Fan, Yiping ^a  

^a University of California   (United States)

Author keywords

Circuits; Energy consumption; Engines; Estimation error; Field programmable gate arrays; High level synthesis; Power generation; Scheduling algorithm; Simulated annealing; Wire

Indexed keywords

ALGORITHMS; BINDING ENERGY; BINS; DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION; ENGINES; ESTIMATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HIGH LEVEL SYNTHESIS; NETWORKS (CIRCUITS); POWER ELECTRONICS; POWER GENERATION; SCHEDULING ALGORITHMS; SIMULATED ANNEALING; SYNTHESIS (CHEMICAL); WIRE;

ESTIMATION ERRORS; FPGA ARCHITECTURES; LOW-POWER DESIGN; POWER CONSUMPTION REDUCTION; POWER ESTIMATIONS; POWER ESTIMATORS; RESOURCE SELECTION FUNCTION; WEIGHTED BIPARTITE MATCHINGS;

LOW POWER ELECTRONICS;

EID: 1542299296     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231849     Document Type: Conference Paper

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